[gcc r16-1179] RISC-V: Support Sstvecd extension.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:a3c4f30ecfc4f7b23df9aa2827068a1bfa57637e commit r16-1179-ga3c4f30ecfc4f7b23df9aa2827068a1bfa57637e Author: Jiawei Date: Thu Jun 5 13:52:08 2025 +0800 RISC-V: Support Sstvecd extension. Support the Sstvecd extension, which allows Supervisor Trap Vector Bas

[gcc r16-1177] RISC-V: Support Sscounterenw extension.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:6a2a0ab8b71e0985f6950f450f8c34437a2fbdcc commit r16-1177-g6a2a0ab8b71e0985f6950f450f8c34437a2fbdcc Author: Jiawei Date: Thu Jun 5 13:33:21 2025 +0800 RISC-V: Support Sscounterenw extension. Support the Sscounterenw extension, which allows writeable enables fo

[gcc r16-1180] RISC-V: Support Ssu64xl extension.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:8e1f06d1d1c8bb25c44c321f90c39f36eb18f344 commit r16-1180-g8e1f06d1d1c8bb25c44c321f90c39f36eb18f344 Author: Jiawei Date: Thu Jun 5 13:59:14 2025 +0800 RISC-V: Support Ssu64xl extension. Support the Ssu64xl extension, which requires UXLEN to be 64. gcc

[gcc r16-1176] RISC-V: Support Ssccptr extension.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:a84b388c84aa7bfed62bf370f3c82d37c943 commit r16-1176-ga84b388c84aa7bfed62bf370f3c82d37c943 Author: Jiawei Date: Thu Jun 5 13:15:02 2025 +0800 RISC-V: Support Ssccptr extension. Support the Ssccptr extension, which allows the main memory to support

[gcc r16-1178] RISC-V: Support Sstvala extension.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:37f0e8395c279b5eb969bf678e5c571c1f3d3b32 commit r16-1178-g37f0e8395c279b5eb969bf678e5c571c1f3d3b32 Author: Jiawei Date: Thu Jun 5 13:46:39 2025 +0800 RISC-V: Support Sstvala extension. Support the Sstvala extension, which provides all needed values in Sup

[gcc r16-1175] RISC-V: Support Smrnmi extension.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:f955831312bbc6426460f18b59a85933bc11ebf4 commit r16-1175-gf955831312bbc6426460f18b59a85933bc11ebf4 Author: Jiawei Date: Thu Jun 5 11:24:43 2025 +0800 RISC-V: Support Smrnmi extension. Support the Smrnmi extension, which provides new CSRs for Machine mode

[gcc r16-1174] RISC-V: Support Sm/scsrind extensions.

2025-06-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:d4129d83135527823730566468ac111067d0dc2d commit r16-1174-gd4129d83135527823730566468ac111067d0dc2d Author: Jiawei Date: Thu Jun 5 10:16:19 2025 +0800 RISC-V: Support Sm/scsrind extensions. Support the Sm/scsrind extensions, which provide indirect access to

[gcc r16-1123] RISC-V: Update extension defination.

2025-06-04 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:d99af4e12bf85048eeef26fb939a97e153ddee9f commit r16-1123-gd99af4e12bf85048eeef26fb939a97e153ddee9f Author: Jiawei Date: Thu Jun 5 09:38:40 2025 +0800 RISC-V: Update extension defination. Update the defination of RISC-V extensions in riscv-ext.def. gc

[gcc r16-1095] RISC-V: Add Shlcofideleg extension.

2025-06-03 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:f8251b4fce20f030fb133de1cadb06f95f01656e commit r16-1095-gf8251b4fce20f030fb133de1cadb06f95f01656e Author: Jiawei Date: Tue May 27 14:37:03 2025 +0800 RISC-V: Add Shlcofideleg extension. This patch add the RISC-V Shlcofideleg extension. It supports delegating

[gcc r16-534] testsuite: Fix RISC-V arch-52.c format issue.

2025-05-11 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:63d26b0e1f11043552404d2ba6448ec74840fa48 commit r16-534-g63d26b0e1f11043552404d2ba6448ec74840fa48 Author: Jiawei Date: Mon May 12 13:23:50 2025 +0800 testsuite: Fix RISC-V arch-52.c format issue. Fix incorrect regular expression. gcc/testsuite/Change

[gcc r16-523] RISC-V: Support RISC-V Profiles 20/22.

2025-05-10 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:43b450e3f72a53c744e77f55393962f1d349373a commit r16-523-g43b450e3f72a53c744e77f55393962f1d349373a Author: Jiawei Date: Sat May 10 20:25:52 2025 +0800 RISC-V: Support RISC-V Profiles 20/22. This patch introduces support for RISC-V Profiles RV20 and RV22 [1],

[gcc r16-524] RISC-V: Support RISC-V Profiles 23.

2025-05-10 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:66d17ba3cb47980455ee9d6b4123dce61aef2fa2 commit r16-524-g66d17ba3cb47980455ee9d6b4123dce61aef2fa2 Author: Jiawei Date: Sat May 10 19:26:35 2025 +0800 RISC-V: Support RISC-V Profiles 23. This patch introduces support for RISC-V Profiles RV23A and RV23B [1],

[gcc r16-492] testsuite: Limit option '-mgeneral-regs-only' backends in pr119160.

2025-05-09 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:61d21863c9cc2e1fe03a4c7231b1119d86243c64 commit r16-492-g61d21863c9cc2e1fe03a4c7231b1119d86243c64 Author: Jiawei Date: Thu May 8 16:50:54 2025 +0800 testsuite: Limit option '-mgeneral-regs-only' backends in pr119160. Limit option '-mgeneral-regs-only' to thos

[gcc r15-3817] hosthooks.h: Fix GCC_HOST_HOOKS_H typo

2024-09-23 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:824229e38662b5921e156d0fcbd7180462ba9d60 commit r15-3817-g824229e38662b5921e156d0fcbd7180462ba9d60 Author: Yangyu Chen Date: Tue Sep 24 01:11:11 2024 +0800 hosthooks.h: Fix GCC_HOST_HOOKS_H typo The comment of the final endif in hosthooks.h is wrong, it shoul

[gcc r15-2809] RISC-V: Minimal support for Zimop extension.

2024-08-07 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:c8f3fdd53871a20838be532b58ef610bf1dd75e1 commit r15-2809-gc8f3fdd53871a20838be532b58ef610bf1dd75e1 Author: Jiawei Date: Fri Aug 2 23:23:14 2024 +0800 RISC-V: Minimal support for Zimop extension. This patch support Zimop and Zcmop extension[1].To enable GCC to

[gcc r15-2781] Fix Wstringop-overflow-47.c warning in RISC-V target.

2024-08-06 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:b4d91abddc2359a5457b1c77f038b86567da52b6 commit r15-2781-gb4d91abddc2359a5457b1c77f038b86567da52b6 Author: Jiawei Date: Tue Jul 16 08:06:25 2024 +0800 Fix Wstringop-overflow-47.c warning in RISC-V target. Update warning test info for RISC-V target, compared o

[gcc r15-2725] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.

2024-08-05 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:70ffc57fd2fdb3c8fa67f11d2e8e6b6275dcc7c0 commit r15-2725-g70ffc57fd2fdb3c8fa67f11d2e8e6b6275dcc7c0 Author: Jiawei Date: Mon Aug 5 20:15:59 2024 +0800 testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50,51. The test has been observed

[gcc r14-10350] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE

2024-06-26 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:6e6f10c3ad6f96752acd9c35b653b387d5c3fcf6 commit r14-10350-g6e6f10c3ad6f96752acd9c35b653b387d5c3fcf6 Author: Jiawei Date: Mon May 27 15:40:51 2024 +0800 tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal speci

[gcc r15-917] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE

2024-05-29 Thread Jiawei Chen via Gcc-cvs
https://gcc.gnu.org/g:c9842f99042454bef99fe82506c6dd50f34e283e commit r15-917-gc9842f99042454bef99fe82506c6dd50f34e283e Author: Jiawei Date: Mon May 27 15:40:51 2024 +0800 tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special