[gcc r16-1177] RISC-V: Support Sscounterenw extension.

[Jiawei Chen via Gcc-cvs]

https://gcc.gnu.org/g:6a2a0ab8b71e0985f6950f450f8c34437a2fbdcc

commit r16-1177-g6a2a0ab8b71e0985f6950f450f8c34437a2fbdcc
Author: Jiawei <jia...@iscas.ac.cn>
Date:   Thu Jun 5 13:33:21 2025 +0800

    RISC-V: Support Sscounterenw extension.
    
    Support the Sscounterenw extension, which allows writeable enables for any
    supported counter.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def: New extension definition.
            * config/riscv/riscv-ext.opt: New extension mask.
            * doc/riscv-ext.texi: Document the new extension.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-sscounterenw.c: New test.
    
    Signed-off-by: Jiawei <jia...@iscas.ac.cn>

Diff:
---
 gcc/config/riscv/riscv-ext.def                     | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                     |  2 ++
 gcc/doc/riscv-ext.texi                             |  4 ++++
 gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c |  5 +++++
 4 files changed, 24 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index ec0a08c3282c..dab8cb8d69d6 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1831,6 +1831,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ sscounterenw,
+  /* UPPERCASE_NAME */ SSCOUNTERENW,
+  /* FULL_NAME */ "Support writeable enables for any supported counter",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ sscsrind,
   /* UPPERCASE_NAME */ SSCSRIND,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index f851678236bd..ad9e1d68069c 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -359,6 +359,8 @@ Mask(SSCCPTR) Var(riscv_ss_subext)
 
 Mask(SSCOFPMF) Var(riscv_ss_subext)
 
+Mask(SSCOUNTERENW) Var(riscv_ss_subext)
+
 Mask(SSCSRIND) Var(riscv_ss_subext)
 
 Mask(SSNPM) Var(riscv_ss_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 83aa436b4665..2b23366607d5 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -542,6 +542,10 @@
 @tab 1.0
 @tab Count overflow & filtering extension
 
+@item sscounterenw
+@tab 1.0
+@tab Support writeable enables for any supported counter
+
 @item sscsrind
 @tab 1.0
 @tab Supervisor-Level Indirect CSR Access
diff --git a/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c 
b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c
new file mode 100644
index 000000000000..901b6bc6c9e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_sscounterenw -mabi=lp64" } */
+int foo()
+{
+}