[gcc r16-1180] RISC-V: Support Ssu64xl extension.

[Jiawei Chen via Gcc-cvs]

https://gcc.gnu.org/g:8e1f06d1d1c8bb25c44c321f90c39f36eb18f344

commit r16-1180-g8e1f06d1d1c8bb25c44c321f90c39f36eb18f344
Author: Jiawei <jia...@iscas.ac.cn>
Date:   Thu Jun 5 13:59:14 2025 +0800

    RISC-V: Support Ssu64xl extension.
    
    Support the Ssu64xl extension, which requires UXLEN to be 64.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def: New extension definition.
            * config/riscv/riscv-ext.opt: New extension mask.
            * doc/riscv-ext.texi: Document the new extension.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-ssu64xl.c: New test.
    
    Signed-off-by: Jiawei <jia...@iscas.ac.cn>

Diff:
---
 gcc/config/riscv/riscv-ext.def                | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                |  2 ++
 gcc/doc/riscv-ext.texi                        |  4 ++++
 gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c |  5 +++++
 4 files changed, 24 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 2b34276fb95e..816acaa34f4a 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1961,6 +1961,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ ssu64xl,
+  /* UPPERCASE_NAME */ SSU64XL,
+  /* FULL_NAME */ "UXLEN=64 must be supported",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ supm,
   /* UPPERCASE_NAME */ SUPM,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 8eb447c2dc01..9f8c5451d497 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -379,6 +379,8 @@ Mask(SSSTRICT) Var(riscv_ss_subext)
 
 Mask(SSDBLTRP) Var(riscv_ss_subext)
 
+Mask(SSU64XL) Var(riscv_ss_subext)
+
 Mask(SUPM) Var(riscv_su_subext)
 
 Mask(SVINVAL) Var(riscv_sv_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index fd9cbef1d9dc..e69a2df768d4 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -582,6 +582,10 @@
 @tab 1.0
 @tab Double Trap Extensions
 
+@item ssu64xl
+@tab 1.0
+@tab UXLEN=64 must be supported
+
 @item supm
 @tab 1.0
 @tab supm extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c 
b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c
new file mode 100644
index 000000000000..6e151c14f9b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_ssu64xl -mabi=lp64" } */
+int foo()
+{
+}