[gcc r16-41] [RISC-V][PR target/119865] Don't free ggc allocated memory

https://gcc.gnu.org/g:1a64b224fa014e772fb30f6bd69ceb24da5827e6 commit r16-41-g1a64b224fa014e772fb30f6bd69ceb24da5827e6 Author: Jeff Law Date: Sat Apr 19 12:35:29 2025 -0600 [RISC-V][PR target/119865] Don't free ggc allocated memory Kaiweng's patch to stop freeing riscv_arch_string

[gcc r16-40] [RISC-V][PR target/118410] Improve code generation for some logical ops

https://gcc.gnu.org/g:874f4c164749f1ed5b60ddf1d4533c8f4ba627a1 commit r16-40-g874f4c164749f1ed5b60ddf1d4533c8f4ba627a1 Author: Jeff Law Date: Sat Apr 19 12:30:42 2025 -0600 [RISC-V][PR target/118410] Improve code generation for some logical ops I'm posting this on behalf of Shreya

[gcc r16-36] [PATCH v2] sh: libgcc: Implement fenv rouding and exceptions for soft-fp [PR118257]

https://gcc.gnu.org/g:05c4e3ecb54d22836ba2ae0ec1efedf8b78d7522 commit r16-36-g05c4e3ecb54d22836ba2ae0ec1efedf8b78d7522 Author: Jiaxun Yang Date: Sat Apr 19 08:12:07 2025 -0600 [PATCH v2] sh: libgcc: Implement fenv rouding and exceptions for soft-fp [PR118257] Implement fenv roudi

[gcc r16-35] [PATCH v2] sh: Correct NaN signalling bit and propagation rules [PR111814]

https://gcc.gnu.org/g:2a643f55f5acc05dcc7cee133647bf3193d5b563 commit r16-35-g2a643f55f5acc05dcc7cee133647bf3193d5b563 Author: Jiaxun Yang Date: Sat Apr 19 08:07:58 2025 -0600 [PATCH v2] sh: Correct NaN signalling bit and propagation rules [PR111814] As per architecture, SuperH ha

[gcc r16-28] [RISC-V] Fix missed bext discovery

https://gcc.gnu.org/g:45a1038f3ca6ddceb8d159ccba6d99ed61951472 commit r16-28-g45a1038f3ca6ddceb8d159ccba6d99ed61951472 Author: Jeff Law Date: Fri Apr 18 12:19:30 2025 -0600 [RISC-V] Fix missed bext discovery RISC-V has the ability to extract a single bit out of a register from a

[gcc r16-21] [PATCH] c6x: Fix EHTYPE relocations

https://gcc.gnu.org/g:baf6ad5dad55a7aa1e75d4ccadc05347b4506a1f commit r16-21-gbaf6ad5dad55a7aa1e75d4ccadc05347b4506a1f Author: Richard Braun Date: Fri Apr 18 09:26:59 2025 -0600 [PATCH] c6x: Fix EHTYPE relocations R_C6000_EHTYPE relocations are implemented as GOT-indirect relocati

[gcc r16-18] [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V)

https://gcc.gnu.org/g:869f2ab30ad53033ad6ac82569d74ce3a99fe510 commit r16-18-g869f2ab30ad53033ad6ac82569d74ce3a99fe510 Author: Hakan Candar Date: Fri Apr 18 07:08:44 2025 -0600 [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V) This produces a toolchain that can succes

[gcc r16-17] [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016]

https://gcc.gnu.org/g:529a43109fcd93f5aafda345da14679f538ada86 commit r16-17-g529a43109fcd93f5aafda345da14679f538ada86 Author: Alexey Merzlyakov Date: Fri Apr 18 06:45:10 2025 -0600 [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016] It fixes one of

[gcc r16-11] [PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch attribute

https://gcc.gnu.org/g:2d6f1ca17f25b28da8f8d83622f0e029da2340e7 commit r16-11-g2d6f1ca17f25b28da8f8d83622f0e029da2340e7 Author: 翁愷邑 Date: Thu Apr 17 16:24:20 2025 -0600 [PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch attribute The build_target_option_node

[gcc r15-9536] [PATCH] rx: avoid adding setpsw for rx_cmpstrn when len is const

https://gcc.gnu.org/g:83340869a21baafc889c05b6b5c632a226c509bc commit r15-9536-g83340869a21baafc889c05b6b5c632a226c509bc Author: Keith Packard Date: Wed Apr 16 14:10:18 2025 -0600 [PATCH] rx: avoid adding setpsw for rx_cmpstrn when len is const pattern using rx_cmpstrn is cmpstrsi

[gcc r15-9385] [committed] [RISC-V] Fix testsuite fallout from recent changes

https://gcc.gnu.org/g:992be16d83814694d6dbce448f9b5cb47ba4c8d4 commit r15-9385-g992be16d83814694d6dbce448f9b5cb47ba4c8d4 Author: Jeff Law Date: Fri Apr 11 08:28:22 2025 -0600 [committed] [RISC-V] Fix testsuite fallout from recent changes Recent changes have started triggering:

[gcc r15-9339] [RISC-V] Fix more fallout from combine.c changes

https://gcc.gnu.org/g:4645d092969face6aa1da4c919924697185f9cf9 commit r15-9339-g4645d092969face6aa1da4c919924697185f9cf9 Author: Jeff Law Date: Wed Apr 9 08:33:17 2025 -0600 [RISC-V] Fix more fallout from combine.c changes Trivial fallout from the recent combine work. We end up w

[gcc r15-9336] [committed][RISC-V] Adjust expected output for rvv test

https://gcc.gnu.org/g:0f74d1e38a7dd1931ab110c2b64b633393393437 commit r15-9336-g0f74d1e38a7dd1931ab110c2b64b633393393437 Author: Jeff Law Date: Wed Apr 9 07:55:06 2025 -0600 [committed][RISC-V] Adjust expected output for rvv test The recent combine changes twiddled code generation

[gcc r15-9160] [PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w

https://gcc.gnu.org/g:dd6ebc0a3473a830115995bdcaf8f797ebd085a3 commit r15-9160-gdd6ebc0a3473a830115995bdcaf8f797ebd085a3 Author: Jin Ma Date: Wed Apr 2 13:37:07 2025 -0600 [PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w Assuming we have the following va

[gcc r15-8241] [RISC-V] Fix unreported code quality regression with single bit manipulations

https://gcc.gnu.org/g:d9a8ec7fe0cbc04e28e650f079952bf529ae612e commit r15-8241-gd9a8ec7fe0cbc04e28e650f079952bf529ae612e Author: Jeff Law Date: Mon Mar 17 17:29:42 2025 -0600 [RISC-V] Fix unreported code quality regression with single bit manipulations I was reviewing some code r

[gcc r15-9038] aarch64: Changed CRC test.

https://gcc.gnu.org/g:df55a933cfc675be2024b16386b96b2807464b41 commit r15-9038-gdf55a933cfc675be2024b16386b96b2807464b41 Author: Mariam Arutunian Date: Sun Mar 30 09:33:39 2025 -0600 aarch64: Changed CRC test. Fixed the iteration number in crc-crc32c-data16.c test from 8 to 16 to

[gcc r15-8245] [RISC-V] Fix another unreported code quality regression

https://gcc.gnu.org/g:e9888795b8bafe37dc65bd638de0533b842c960a commit r15-8245-ge9888795b8bafe37dc65bd638de0533b842c960a Author: Jeff Law Date: Mon Mar 17 21:58:03 2025 -0600 [RISC-V] Fix another unreported code quality regression So here's the other case I was just looking at. T

[gcc r15-8080] [RISC-V][PR target/116256][V4] Fix minor code quality regression in reassociated arithmetic

https://gcc.gnu.org/g:9d68a2a67351fc5b56262c0028ef8fd1d1466627 commit r15-8080-g9d68a2a67351fc5b56262c0028ef8fd1d1466627 Author: Jeff Law Date: Sun Mar 16 17:43:48 2025 -0600 [RISC-V][PR target/116256][V4] Fix minor code quality regression in reassociated arithmetic Arggh. This

[gcc r15-7916] [rtl-optimization/117467] Mark FP destinations as dead

https://gcc.gnu.org/g:7d3aec2a832ef47be547d9426187562e4548bae6 commit r15-7916-g7d3aec2a832ef47be547d9426187562e4548bae6 Author: Jeff Law Date: Sun Mar 9 14:25:37 2025 -0600 [rtl-optimization/117467] Mark FP destinations as dead The next step in improving ext-dce is to clean up a

[gcc r15-7977] Revert "[rtl-optimization/117467] Avoid unnecessarily marking things live in ext-dce"

https://gcc.gnu.org/g:9cebf1234b88e55a04071bd55c9ec4e22c0899e6 commit r15-7977-g9cebf1234b88e55a04071bd55c9ec4e22c0899e6 Author: Jeff Law Date: Tue Mar 11 18:01:33 2025 -0600 Revert "[rtl-optimization/117467] Avoid unnecessarily marking things live in ext-dce" This reverts commit

[gcc r15-7915] [rtl-optimization/117467] Avoid unnecessarily marking things live in ext-dce

https://gcc.gnu.org/g:4ed07a11ee2845c2085a3cd5cff043209a452441 commit r15-7915-g4ed07a11ee2845c2085a3cd5cff043209a452441 Author: Jeff Law Date: Sun Mar 9 13:28:10 2025 -0600 [rtl-optimization/117467] Avoid unnecessarily marking things live in ext-dce This is the first of what I ex

[gcc r15-7874] [PR rtl-optimization/119099] Avoid infinite loop in ext-dce.

https://gcc.gnu.org/g:aef04968cfba0feb4420d96c61f766ee6c73f957 commit r15-7874-gaef04968cfba0feb4420d96c61f766ee6c73f957 Author: Alexey Merzlyakov Date: Thu Mar 6 14:42:59 2025 -0700 [PR rtl-optimization/119099] Avoid infinite loop in ext-dce. This fixes the ping-ponging of live s

[gcc r15-7847] Improve coverage of ext-dce tests in risc-v testsuite

https://gcc.gnu.org/g:316eaca17ee11f575fc72e139e8cc3f9f5ccb067 commit r15-7847-g316eaca17ee11f575fc72e139e8cc3f9f5ccb067 Author: Jeff Law Date: Wed Mar 5 22:24:05 2025 -0700 Improve coverage of ext-dce tests in risc-v testsuite Inspired by Liao Shihua, this adjusts two tests in th

[gcc r13-9406] [PR target/116720] Fix test for valid mempair operands

https://gcc.gnu.org/g:e00c33df5d64990197b2382399a2a8b80b994176 commit r13-9406-ge00c33df5d64990197b2382399a2a8b80b994176 Author: Jeff Law Date: Sun Dec 29 08:27:30 2024 -0700 [PR target/116720] Fix test for valid mempair operands So this BZ is a case where we incorrectly indicated

[gcc r14-11371] [PR target/116720] Fix test for valid mempair operands

https://gcc.gnu.org/g:c1535f242f703d3142bef1ca7c31d1ee17633696 commit r14-11371-gc1535f242f703d3142bef1ca7c31d1ee17633696 Author: Jeff Law Date: Sun Dec 29 08:27:30 2024 -0700 [PR target/116720] Fix test for valid mempair operands So this BZ is a case where we incorrectly indicate

[gcc r15-7787] [RISC-V][PR target/118934] Fix ICE in RISC-V long branch support

https://gcc.gnu.org/g:67e824c2497176980cb0c5d14bc730fa4ce2e1ad commit r15-7787-g67e824c2497176980cb0c5d14bc730fa4ce2e1ad Author: Jeff Law Date: Sun Mar 2 12:08:34 2025 -0700 [RISC-V][PR target/118934] Fix ICE in RISC-V long branch support I'm not sure if I goof'd this or if I mere

[gcc r15-7774] [PR target/118906] [PATCH v2] RISC-V: Fix a typo in zce to zcf implication

https://gcc.gnu.org/g:a0d29dd218e7d96f0715360a2ab6fdd8dc9b3446 commit r15-7774-ga0d29dd218e7d96f0715360a2ab6fdd8dc9b3446 Author: Yuriy Kolerov Date: Sat Mar 1 08:35:55 2025 -0700 [PR target/118906] [PATCH v2] RISC-V: Fix a typo in zce to zcf implication zce must imply zcf but this

[gcc r15-7773] [PATCH] H8/300, libgcc: PR target/114222 For HImode call internal ffs() implementation instead of an

https://gcc.gnu.org/g:898f22d15805229a932fff7f22a0a8054e1b9b31 commit r15-7773-g898f22d15805229a932fff7f22a0a8054e1b9b31 Author: Jan Dubiec Date: Sat Mar 1 08:21:16 2025 -0700 [PATCH] H8/300, libgcc: PR target/114222 For HImode call internal ffs() implementation instead of an external one

[gcc r15-7768] [PATCH] H8/300: PR target/109189 Silence -Wformat warnings on Windows

https://gcc.gnu.org/g:2fc17730dcef182bba3c9d4e32fc00302ef421fe commit r15-7768-g2fc17730dcef182bba3c9d4e32fc00302ef421fe Author: Jan Dubiec Date: Fri Feb 28 22:01:42 2025 -0700 [PATCH] H8/300: PR target/109189 Silence -Wformat warnings on Windows This patch fixes annoying -Wformat

[gcc r15-7614] [PR middle-end/113525] Drop obsolete options from documentation

https://gcc.gnu.org/g:3e93035fcc9247928b58443e37fbf844278b7ac7 commit r15-7614-g3e93035fcc9247928b58443e37fbf844278b7ac7 Author: Jeff Law Date: Tue Feb 18 19:45:29 2025 -0700 [PR middle-end/113525] Drop obsolete options from documentation The sibling and unshare passes were droppe

[gcc r15-7579] [PR target/118248] Avoid bogus alloca call in RISC-V backend

https://gcc.gnu.org/g:68e74199c61c5ad81ffe37e41cd62d0d7415b3ab commit r15-7579-g68e74199c61c5ad81ffe37e41cd62d0d7415b3ab Author: Jakub Jelinek Date: Sun Feb 16 11:19:20 2025 -0700 [PR target/118248] Avoid bogus alloca call in RISC-V backend This is Jakub's patch and Ian's testcase

[gcc r15-7571] [PR tree-optimization/98028] Use relationship between operands to simplify SUB_OVERFLOW

https://gcc.gnu.org/g:42a22b801d4ad654e420495fafc4d29d113f00eb commit r15-7571-g42a22b801d4ad654e420495fafc4d29d113f00eb Author: Jakub Jelinek Date: Sat Feb 15 16:45:21 2025 -0700 [PR tree-optimization/98028] Use relationship between operands to simplify SUB_OVERFLOW So this is a

[gcc r15-7568] [PATCH] RISC-V: Fix some widen-complicate tests.

https://gcc.gnu.org/g:d7a835a5309db81a129b0151c7e5deb25b0ec55c commit r15-7568-gd7a835a5309db81a129b0151c7e5deb25b0ec55c Author: Robin Dapp Date: Sat Feb 15 09:21:34 2025 -0700 [PATCH] RISC-V: Fix some widen-complicate tests. this patch adds two bridge patterns for combine in orde

[gcc r15-7567] [PATCH] rx: allow cmpstrnsi len to be zero

https://gcc.gnu.org/g:11cc336eed42892b7cfc2bfcf7b3f3f86f61787a commit r15-7567-g11cc336eed42892b7cfc2bfcf7b3f3f86f61787a Author: Keith Packard Date: Sat Feb 15 09:17:41 2025 -0700 [PATCH] rx: allow cmpstrnsi len to be zero The SCMPU instruction doesn't change the C and Z flags whe

[gcc r15-7566] [PATCH] RISC-V: testsuite: Adjust pr117722.c scan.

https://gcc.gnu.org/g:f9868e623fc80c6c6260c9dc6c7280db90433207 commit r15-7566-gf9868e623fc80c6c6260c9dc6c7280db90433207 Author: Robin Dapp Date: Sat Feb 15 08:48:06 2025 -0700 [PATCH] RISC-V: testsuite: Adjust pr117722.c scan. the test scanned for vmin and vmax instead of vminu a

[gcc r15-7565] RISC-V: testsuite: Fix reduc-[89].c again.

https://gcc.gnu.org/g:ad3de70fd863e32ea6440bcb613ffe2c58c2dae8 commit r15-7565-gad3de70fd863e32ea6440bcb613ffe2c58c2dae8 Author: Robin Dapp Date: Sat Feb 15 08:44:51 2025 -0700 RISC-V: testsuite: Fix reduc-[89].c again. my last fix wasn't sufficient. This patch just scans for the

[gcc r15-7516] RISC-V: Avoid more unsplit insns in const expander [PR118832].

https://gcc.gnu.org/g:28b2ad5341f875ee7e034b0c6f9e4eb725e19a8f commit r15-7516-g28b2ad5341f875ee7e034b0c6f9e4eb725e19a8f Author: Robin Dapp Date: Thu Feb 13 16:33:24 2025 -0700 RISC-V: Avoid more unsplit insns in const expander [PR118832]. Hi, in PR118832 we have another

[gcc r15-7485] RISC-V: Drop __riscv_vendor_feature_bits

https://gcc.gnu.org/g:2605daa6b896aed15dead194462725874f332c0a commit r15-7485-g2605daa6b896aed15dead194462725874f332c0a Author: Yangyu Chen Date: Tue Feb 11 18:40:41 2025 -0700 RISC-V: Drop __riscv_vendor_feature_bits As discussed from RISC-V C-API PR #101 [1], As discussed in #9

[gcc r15-7483] [PR target/115478] Accept ADD, IOR or XOR when combining objects with no bits in common

https://gcc.gnu.org/g:71f6540fc54036cc8f71db497cc22816f794549a commit r15-7483-g71f6540fc54036cc8f71db497cc22816f794549a Author: Jeff Law Date: Tue Feb 11 16:55:03 2025 -0700 [PR target/115478] Accept ADD, IOR or XOR when combining objects with no bits in common So the change to

[gcc r15-7451] [PR target/115123] Fix testsuite fallout from sinking heuristic change

https://gcc.gnu.org/g:22e30d60b971eed9a4754ea920d05b1b7e89090a commit r15-7451-g22e30d60b971eed9a4754ea920d05b1b7e89090a Author: Jeff Law Date: Sun Feb 9 09:55:56 2025 -0700 [PR target/115123] Fix testsuite fallout from sinking heuristic change Code sinking is just semantic preser

[gcc r15-7450] [PR middle-end/117263] Avoid unused-but-set warning in genautomata

https://gcc.gnu.org/g:b81bb3ed216213fdaba82addae9fc34619ad6ec7 commit r15-7450-gb81bb3ed216213fdaba82addae9fc34619ad6ec7 Author: Dario Gjorgjevski Date: Sun Feb 9 09:16:31 2025 -0700 [PR middle-end/117263] Avoid unused-but-set warning in genautomata This is a trivial bug where a u

[gcc r15-7448] [RISC-V][PR target/118146] Fix ICE for unsupported modes

https://gcc.gnu.org/g:9576353454e6c2a20a9742e2f29f17830766cd8a commit r15-7448-g9576353454e6c2a20a9742e2f29f17830766cd8a Author: Jeff Law Date: Sat Feb 8 22:07:16 2025 -0700 [RISC-V][PR target/118146] Fix ICE for unsupported modes There's some special case code in the risc-v move

[gcc r15-7428] [rtl-optimization/116244] Don't create bogus regs in alter_subreg

https://gcc.gnu.org/g:388910144a3f11ba61208fc80afb2fa78d657163 commit r15-7428-g388910144a3f11ba61208fc80afb2fa78d657163 Author: Jeff Law Date: Fri Feb 7 09:10:59 2025 -0700 [rtl-optimization/116244] Don't create bogus regs in alter_subreg > Jeff Law writes: >> So pulling on

[gcc r15-7398] [PATCH] RISC-V: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST to correct enum

https://gcc.gnu.org/g:ba585064781b58eef4667c0baa09b854f711aae4 commit r15-7398-gba585064781b58eef4667c0baa09b854f711aae4 Author: Craig Blackmore Date: Thu Feb 6 12:56:26 2025 -0700 [PATCH] RISC-V: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST to correct enum stack_protect_{set,test}_ we

[gcc r15-7397] [RISC-V] Fix risc-v expected test output after recent iv changes

https://gcc.gnu.org/g:33e610110c933b0d65aa82d67864bb881768609f commit r15-7397-g33e610110c933b0d65aa82d67864bb881768609f Author: Jeff Law Date: Thu Feb 6 12:37:11 2025 -0700 [RISC-V] Fix risc-v expected test output after recent iv changes Richard S's recent change to iv increment

[gcc r15-7381] [committed] Disable ABS instruction on bfin port

https://gcc.gnu.org/g:3e08a4ecea27c54fda90e8f58641b1986ad957e1 commit r15-7381-g3e08a4ecea27c54fda90e8f58641b1986ad957e1 Author: Jeff Law Date: Wed Feb 5 14:22:33 2025 -0700 [committed] Disable ABS instruction on bfin port I was looking at a regression on the bfin port with a rece

[gcc r15-7313] [committed][PR tree-optimization/114277] Fix missed optimization for multiplication against boolean

https://gcc.gnu.org/g:2c0a9b7fb7902522fb8484342fcc19fd44df53e6 commit r15-7313-g2c0a9b7fb7902522fb8484342fcc19fd44df53e6 Author: Jeff Law Date: Fri Jan 31 16:59:35 2025 -0700 [committed][PR tree-optimization/114277] Fix missed optimization for multiplication against boolean value

[gcc r15-7281] [PR testsuite/116860] Testsuite adjustment for recently added tests

https://gcc.gnu.org/g:15dba7dfba8b7800ac7b74213171e4df9bc32bb9 commit r15-7281-g15dba7dfba8b7800ac7b74213171e4df9bc32bb9 Author: Jeff Law Date: Wed Jan 29 19:42:11 2025 -0700 [PR testsuite/116860] Testsuite adjustment for recently added tests There's two new tests that are depende

[gcc r15-7273] [PATCH] RX: Restrict displacement ranges in "Q" constraint

https://gcc.gnu.org/g:4318821562638a3d909942f561a42f7272ddfed4 commit r15-7273-g4318821562638a3d909942f561a42f7272ddfed4 Author: Yoshinori Sato Date: Wed Jan 29 08:07:15 2025 -0700 [PATCH] RX: Restrict displacement ranges in "Q" constraint When using the "Q" constraint in the inli

[gcc r15-7242] [PR target/114085] Fix H8 constraint issue which led to ICE

https://gcc.gnu.org/g:235215323c67d8ce021a00df0f42e2c1713c7959 commit r15-7242-g235215323c67d8ce021a00df0f42e2c1713c7959 Author: Jeff Law Date: Mon Jan 27 21:25:39 2025 -0700 [PR target/114085] Fix H8 constraint issue which led to ICE Nowhere near the top of my list, but a quick l

[gcc r15-7208] [RISC-V][PR target/116256] Improve handling of single bit constants

https://gcc.gnu.org/g:e5990a6ce611f522b8f48c2b469983da19d39777 commit r15-7208-ge5990a6ce611f522b8f48c2b469983da19d39777 Author: Jeff Law Date: Sat Jan 25 09:42:19 2025 -0700 [RISC-V][PR target/116256] Improve handling of single bit constants So under the umbrella of pr116256 (P3

[gcc r15-7115] Revert "[PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions"

https://gcc.gnu.org/g:d4a1a63fc4fbfb7ed92862cd8befc7bef2bc602b commit r15-7115-gd4a1a63fc4fbfb7ed92862cd8befc7bef2bc602b Author: Jeff Law Date: Tue Jan 21 16:20:16 2025 -0700 Revert "[PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions" This reverts commit b22d9c8f8216d1

[gcc r15-7116] Revert "[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions"

https://gcc.gnu.org/g:3f641a8f1d1fafc0c6531aee185d0e74998987d5 commit r15-7116-g3f641a8f1d1fafc0c6531aee185d0e74998987d5 Author: Jeff Law Date: Tue Jan 21 16:21:44 2025 -0700 Revert "[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions" This reverts commit d2c8548e0ce5

[gcc r15-7107] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero immediate

https://gcc.gnu.org/g:3024b12f2cde5db3bf52b49b07e32ef3065929fb commit r15-7107-g3024b12f2cde5db3bf52b49b07e32ef3065929fb Author: Jin Ma Date: Tue Jan 21 10:46:37 2025 -0700 RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero immediate Althou

[gcc r15-7106] RISC-V: Enable and adjust the testsuite for XTheadVector.

https://gcc.gnu.org/g:ab24171d237a9138714f0e6d2bb38fd357ccaed9 commit r15-7106-gab24171d237a9138714f0e6d2bb38fd357ccaed9 Author: Jin Ma Date: Tue Jan 21 10:43:47 2025 -0700 RISC-V: Enable and adjust the testsuite for XTheadVector. gcc/testsuite/ChangeLog: * gcc.ta

[gcc r15-7100] [RISC-V][PR target/116256] Fix incorrect return value for predicate

https://gcc.gnu.org/g:61995d86b66b39698c0dfbbab8d8dca579b42d00 commit r15-7100-g61995d86b66b39698c0dfbbab8d8dca579b42d00 Author: Jeff Law Date: Tue Jan 21 06:56:27 2025 -0700 [RISC-V][PR target/116256] Fix incorrect return value for predicate Another bug found while chasing paths

[gcc r15-7082] [PR target/116256] Adjust expected output in a couple testcases

https://gcc.gnu.org/g:1edd93fbaddce9b2938e2927014272fa621ade9c commit r15-7082-g1edd93fbaddce9b2938e2927014272fa621ade9c Author: Jeff Law Date: Mon Jan 20 15:05:34 2025 -0700 [PR target/116256] Adjust expected output in a couple testcases I've had a long standing TODO to review th

[gcc r15-7081] [PR target/114442] Add reservations for all insn types to xiangshan-nanhu model

https://gcc.gnu.org/g:64a162d5562a333b816f6dc188814c14ba3c9f2c commit r15-7081-g64a162d5562a333b816f6dc188814c14ba3c9f2c Author: Jeff Law Date: Mon Jan 20 14:50:57 2025 -0700 [PR target/114442] Add reservations for all insn types to xiangshan-nanhu model The RISC-V backend has ch

[gcc r15-7080] [PR target/116256] Fix latent regression in pattern to associate arithmetic to simplify constants

https://gcc.gnu.org/g:59e5d086a348f2b9e5adae1ba820ba7aaf7289db commit r15-7080-g59e5d086a348f2b9e5adae1ba820ba7aaf7289db Author: Jeff Law Date: Mon Jan 20 14:35:59 2025 -0700 [PR target/116256] Fix latent regression in pattern to associate arithmetic to simplify constants This is

[gcc r15-7068] RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov

https://gcc.gnu.org/g:9d869296f095a02c37d3721f546ce99663e5417c commit r15-7068-g9d869296f095a02c37d3721f546ce99663e5417c Author: Jin Ma Date: Mon Jan 20 09:29:30 2025 -0700 RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov For XTheadCondMov, the bit w

[gcc r15-7025] [RISC-V][PR target/116308] Fix generation of initial RTL for atomics

https://gcc.gnu.org/g:deb3a4ae5dc04616dff893de074de0797594c98e commit r15-7025-gdeb3a4ae5dc04616dff893de074de0797594c98e Author: Jeff Law Date: Sat Jan 18 13:44:33 2025 -0700 [RISC-V][PR target/116308] Fix generation of initial RTL for atomics While this wasn't originally marked a

[gcc r15-7022] RISC-V: Disable RV64-only crc testcases for RV32

https://gcc.gnu.org/g:729591f1017bf72f924d2bb6ebbad202da95171d commit r15-7022-g729591f1017bf72f924d2bb6ebbad202da95171d Author: Bohan Lei Date: Sat Jan 18 08:09:48 2025 -0700 RISC-V: Disable RV64-only crc testcases for RV32 These testcases require RV64 targets. They fail when -m

[gcc r15-7021] [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XThead

https://gcc.gnu.org/g:b9493e98da58c7689645b4ee1a2f653b86a5d758 commit r15-7021-gb9493e98da58c7689645b4ee1a2f653b86a5d758 Author: Jin Ma Date: Sat Jan 18 07:43:17 2025 -0700 [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XTheadVector.

[gcc r15-6938] lm32: In va_arg, skip to stack args with too few remaining reg args

https://gcc.gnu.org/g:cf9de710aaacd8a3c2cddf348c704b19a5404a0f commit r15-6938-gcf9de710aaacd8a3c2cddf348c704b19a5404a0f Author: Keith Packard Date: Wed Jan 15 22:11:01 2025 -0700 lm32: In va_arg, skip to stack args with too few remaining reg args lm32 has 8 register parameter slo

[gcc r15-6937] lm32: Compute pretend_size in setup_incoming_varargs even if no_rtl

https://gcc.gnu.org/g:423e9a8ad59e6972cd6f25238cd328080fed11cc commit r15-6937-g423e9a8ad59e6972cd6f25238cd328080fed11cc Author: Keith Packard Date: Wed Jan 15 22:08:59 2025 -0700 lm32: Compute pretend_size in setup_incoming_varargs even if no_rtl gcc/ * config/lm32/lm

[gcc r15-6936] lm32: Skip last named param when computing save varargs regs

https://gcc.gnu.org/g:6e593fcda49b1001e87e94ab709607b4fb2c66cf commit r15-6936-g6e593fcda49b1001e87e94ab709607b4fb2c66cf Author: Keith Packard Date: Wed Jan 15 22:05:46 2025 -0700 lm32: Skip last named param when computing save varargs regs The cumulative args value in setup_incom

[gcc r15-6935] lm32: Args with arg.named false still get passed in regs

https://gcc.gnu.org/g:3184f6a565ed5efab39faf9eee764f393c74442d commit r15-6935-g3184f6a565ed5efab39faf9eee764f393c74442d Author: Keith Packard Date: Wed Jan 15 22:02:36 2025 -0700 lm32: Args with arg.named false still get passed in regs * config/lm32/lm32.cc (lm32_function

[gcc r15-6903] [RISC-V][PR target/118170] Add HF div/sqrt reservation

https://gcc.gnu.org/g:d6f1961e68092fda35ce064ef45d1dbec780c624 commit r15-6903-gd6f1961e68092fda35ce064ef45d1dbec780c624 Author: Anton Blanchard Date: Tue Jan 14 22:11:13 2025 -0700 [RISC-V][PR target/118170] Add HF div/sqrt reservation Clearly an oversight in the generic-ooo mode

[gcc r15-6902] [PR rtl-optimization/109592] Simplify nested shifts

https://gcc.gnu.org/g:cab2e12362287bd50f9abdd7fb5a775138e02d1b commit r15-6902-gcab2e12362287bd50f9abdd7fb5a775138e02d1b Author: Richard Sandiford Date: Tue Jan 14 21:51:41 2025 -0700 [PR rtl-optimization/109592] Simplify nested shifts > The BZ in question is a failure to recogniz

[gcc r15-6884] RISC-V: Expand shift count in Xmode in interleave pattern.

https://gcc.gnu.org/g:c864ffe615424de08abfe271fee7dc815c93bd21 commit r15-6884-gc864ffe615424de08abfe271fee7dc815c93bd21 Author: Robin Dapp Date: Mon Jan 13 17:19:42 2025 -0700 RISC-V: Expand shift count in Xmode in interleave pattern. Hi, currently ssa-dse-1.C ICEs becau

[gcc r15-6881] RISC-V: Disallow negative step for interleaving [PR117682]

https://gcc.gnu.org/g:7b815107f403c526b7e201ca00494f06d1c20768 commit r15-6881-g7b815107f403c526b7e201ca00494f06d1c20768 Author: Robin Dapp Date: Mon Jan 13 17:09:35 2025 -0700 RISC-V: Disallow negative step for interleaving [PR117682] Hi, in PR117682 we build an interlea

[gcc r15-6880] RISC-V: testsuite: Skip test with -flto

https://gcc.gnu.org/g:1f6453684696b1c18899cbbecd4bd5ed4ae22476 commit r15-6880-g1f6453684696b1c18899cbbecd4bd5ed4ae22476 Author: Robin Dapp Date: Mon Jan 13 16:26:24 2025 -0700 RISC-V: testsuite: Skip test with -flto Hi, the zbb-rol-ror and stack_save_restore tests use th

[gcc r15-6877] RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921]

https://gcc.gnu.org/g:a9ebf249063d2e8f6e8813fc954276766ad3a2fe commit r15-6877-ga9ebf249063d2e8f6e8813fc954276766ad3a2fe Author: Xi Ruoyao Date: Mon Jan 13 13:11:38 2025 -0700 RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921] The test case long

[gcc r15-6874] RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921]

https://gcc.gnu.org/g:107d5d682576e54963ddd36f3f21bc6b9506d278 commit r15-6874-g107d5d682576e54963ddd36f3f21bc6b9506d278 Author: Xi Ruoyao Date: Mon Jan 13 11:28:05 2025 -0700 RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921] When z

[gcc r15-6873] RISC-V: Fix the result error caused by not updating ratio when using "use_max_sew" to merge vsetvl

https://gcc.gnu.org/g:8d577a01cdbe02a23724b710b579b7811c983c33 commit r15-6873-g8d577a01cdbe02a23724b710b579b7811c983c33 Author: Jin Ma Date: Mon Jan 13 11:15:55 2025 -0700 RISC-V: Fix the result error caused by not updating ratio when using "use_max_sew" to merge vsetvl When the

[gcc r15-6870] RISC-V: Fix program logic errors caused by data truncation on 32-bit host for zbs, such as i386

https://gcc.gnu.org/g:ecf688edc217472774817cc1284e75a9f72fe1b4 commit r15-6870-gecf688edc217472774817cc1284e75a9f72fe1b4 Author: Jin Ma Date: Mon Jan 13 10:10:22 2025 -0700 RISC-V: Fix program logic errors caused by data truncation on 32-bit host for zbs, such as i386 Correct log

[gcc r15-6867] [PR rtl-optimization/107455] Eliminate unnecessary constant load

https://gcc.gnu.org/g:d23d338da4d2bd581b2d3fd97785dd2c26053a92 commit r15-6867-gd23d338da4d2bd581b2d3fd97785dd2c26053a92 Author: Jeff Law Date: Mon Jan 13 07:29:39 2025 -0700 [PR rtl-optimization/107455] Eliminate unnecessary constant load This resurrects a patch from a bit over 2

[gcc r15-6843] [PATCH] crc: Fix up some crc related wrong code issues [PR117997, PR118415]

https://gcc.gnu.org/g:9c387a99a911724546abe99ecd39bfc968ed6333 commit r15-6843-g9c387a99a911724546abe99ecd39bfc968ed6333 Author: Jakub Jelinek Date: Sun Jan 12 17:24:53 2025 -0700 [PATCH] crc: Fix up some crc related wrong code issues [PR117997, PR118415] Hi! As mentioned

[gcc r15-6672] [PATCH] libgcc/m68k: More fixes for soft float

https://gcc.gnu.org/g:0115ef57efa9966fa7f448185dd5c741f58d4fac commit r15-6672-g0115ef57efa9966fa7f448185dd5c741f58d4fac Author: Keith Packard Date: Tue Jan 7 14:54:11 2025 -0700 [PATCH] libgcc/m68k: More fixes for soft float Fix __extenddfxf2: * Remove bogus denorm han

[gcc r15-6671] Prefer scalar_int_mode if the size - 1 is equal to UNITS_PER_WORD.

https://gcc.gnu.org/g:d953c2c5714ed8503c4ae1b7d059a62e4e9a0624 commit r15-6671-gd953c2c5714ed8503c4ae1b7d059a62e4e9a0624 Author: Tsung Chun Lin Date: Tue Jan 7 14:48:31 2025 -0700 Prefer scalar_int_mode if the size - 1 is equal to UNITS_PER_WORD. Don't use the QI vector if its siz

[gcc r15-6670] Fix testsuite expectations for RVV after recent change

https://gcc.gnu.org/g:c6b5398e9e3c387910e1736f06525a0724a84b3e commit r15-6670-gc6b5398e9e3c387910e1736f06525a0724a84b3e Author: Jeff Law Date: Tue Jan 7 14:27:28 2025 -0700 Fix testsuite expectations for RVV after recent change Tamar's recent improvement to improve affine unsigne

[gcc r15-6668] [PATCH] riscv: add mising masking in lrsc expander (PR118137)

https://gcc.gnu.org/g:013e66ea95a241c472b9d87430efaf6c759cf5c0 commit r15-6668-g013e66ea95a241c472b9d87430efaf6c759cf5c0 Author: Andreas Schwab Date: Tue Jan 7 12:23:37 2025 -0700 [PATCH] riscv: add mising masking in lrsc expander (PR118137) gcc: PR target/118137

[gcc r15-6669] [PATCH] testsuite: enable effective-target sync_char_short on RISC-V

https://gcc.gnu.org/g:e8a3f6bfb8d92756bc33c3a520bca1ff644d64b7 commit r15-6669-ge8a3f6bfb8d92756bc33c3a520bca1ff644d64b7 Author: Andreas Schwab Date: Tue Jan 7 12:31:39 2025 -0700 [PATCH] testsuite: enable effective-target sync_char_short on RISC-V gcc/testuite/ * lib/

[gcc r15-6667] Fix regression in ft32 port after recent switch table adjustments

https://gcc.gnu.org/g:a550edc3fae828cef67aac050b80179a97bb2fad commit r15-6667-ga550edc3fae828cef67aac050b80179a97bb2fad Author: Jeff Law Date: Tue Jan 7 12:20:15 2025 -0700 Fix regression in ft32 port after recent switch table adjustments This is a trivial bug that showed up afte

[gcc r15-6653] [PR testsuite/118055] Trivial testsuite adjustment for m68k target

https://gcc.gnu.org/g:a856b4d97b8d328fdcb169b792ac5456e40f8c00 commit r15-6653-ga856b4d97b8d328fdcb169b792ac5456e40f8c00 Author: Jeff Law Date: Tue Jan 7 07:43:19 2025 -0700 [PR testsuite/118055] Trivial testsuite adjustment for m68k target After a bit of a prod from Hans...

[gcc r15-6650] RISC-V: Add missing dg-runtest to run the testcase under gcc.target/riscv/rvv/

https://gcc.gnu.org/g:bacaf016aa3f40a7a9a3fd96c4f8bebb5312f6a3 commit r15-6650-gbacaf016aa3f40a7a9a3fd96c4f8bebb5312f6a3 Author: Tsung Chun Lin Date: Tue Jan 7 07:07:23 2025 -0700 RISC-V: Add missing dg-runtest to run the testcase under gcc.target/riscv/rvv/ gcc/testsuite/ChangeL

[gcc r15-6476] [PATCH v2] varasm: Use native_encode_rtx for constant vectors.

https://gcc.gnu.org/g:509df13fbf0b3544cd39a9e0a5de11ce841bb185 commit r15-6476-g509df13fbf0b3544cd39a9e0a5de11ce841bb185 Author: Robin Dapp Date: Mon Dec 30 23:47:53 2024 -0700 [PATCH v2] varasm: Use native_encode_rtx for constant vectors. optimize_constant_pool hashes vector mask

[gcc r15-6475] [RISC-V][PR target/115375] Fix expected dump output

https://gcc.gnu.org/g:d369ddca549b5ff7d868b8f5ee139835b1f9382a commit r15-6475-gd369ddca549b5ff7d868b8f5ee139835b1f9382a Author: Jeff Law Date: Mon Dec 30 23:40:58 2024 -0700 [RISC-V][PR target/115375] Fix expected dump output Several months ago changes were made to the vectorizer

[gcc r15-6473] [PR testsuite/114182] Fix minor testsuite issue when double == float

https://gcc.gnu.org/g:b739efa05d96edbc1468043a630bf29d38a0c30b commit r15-6473-gb739efa05d96edbc1468043a630bf29d38a0c30b Author: Jeff Law Date: Mon Dec 30 16:14:29 2024 -0700 [PR testsuite/114182] Fix minor testsuite issue when double == float This is a minor testsuite adjustment

[gcc r15-6472] [RISC-V][PR target/106544] Avoid ICEs due to bogus asms

https://gcc.gnu.org/g:07e532a0608640b9e57ae6fc3a0ca83c9afc75a1 commit r15-6472-g07e532a0608640b9e57ae6fc3a0ca83c9afc75a1 Author: Jeff Law Date: Mon Dec 30 13:51:55 2024 -0700 [RISC-V][PR target/106544] Avoid ICEs due to bogus asms This is a fix for a bug Andrew P filed a while bac

[gcc r15-6470] [RISC-V][PR target/118122] Fix modes in recently added risc-v pattern

https://gcc.gnu.org/g:64d31343d4676d8ceef9232dcd33824bc2eff330 commit r15-6470-g64d31343d4676d8ceef9232dcd33824bc2eff330 Author: Jeff Law Date: Mon Dec 30 07:40:07 2024 -0700 [RISC-V][PR target/118122] Fix modes in recently added risc-v pattern The new pattern to optimize certain

[gcc r15-6460] [RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern

https://gcc.gnu.org/g:7cea821aaceeec9a6a960392f49346d52d1bd54a commit r15-6460-g7cea821aaceeec9a6a960392f49346d52d1bd54a Author: Jeff Law Date: Sun Dec 29 16:34:52 2024 -0700 [RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern So for this bug we have what appears to me

[gcc r15-6458] [PR target/116720] Fix test for valid mempair operands

https://gcc.gnu.org/g:0b06abe027a78681d29a5e91daa74bf8dba39826 commit r15-6458-g0b06abe027a78681d29a5e91daa74bf8dba39826 Author: Jeff Law Date: Sun Dec 29 08:27:30 2024 -0700 [PR target/116720] Fix test for valid mempair operands So this BZ is a case where we incorrectly indicated

[gcc r15-6407] [RISC-V][PR middle-end/118084] Fix brev based reflection code

https://gcc.gnu.org/g:145e462d557af537d90ef6da1391a57603c6fcf0 commit r15-6407-g145e462d557af537d90ef6da1391a57603c6fcf0 Author: Jeff Law Date: Sat Dec 21 08:33:36 2024 -0700 [RISC-V][PR middle-end/118084] Fix brev based reflection code The fuzzer tripped over a risc-v target issu

[gcc r15-6306] RISC-V: Remove svvptc from riscv-ext-bitmask.def

https://gcc.gnu.org/g:d24a5e2d381b290d4def659ed83e969b65d07f02 commit r15-6306-gd24a5e2d381b290d4def659ed83e969b65d07f02 Author: Yangyu Chen Date: Tue Dec 17 07:41:05 2024 -0700 RISC-V: Remove svvptc from riscv-ext-bitmask.def There should be no svvptc in the riscv-ext-bitmask.def

[gcc r15-6307] [PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)

https://gcc.gnu.org/g:d17b09c07a1da0e3950718aabc2cbdb90cae402b commit r15-6307-gd17b09c07a1da0e3950718aabc2cbdb90cae402b Author: Oliver Kozul Date: Tue Dec 17 07:44:33 2024 -0700 [PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val) The patch optimizes cod

[gcc r15-6304] [PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture

https://gcc.gnu.org/g:4aa01ecc5c1389d1cdf5721b936993ba17b96178 commit r15-6304-g4aa01ecc5c1389d1cdf5721b936993ba17b96178 Author: Anton Blanchard Date: Tue Dec 17 07:34:20 2024 -0700 [PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture This adds the Tenstorrent Ascalo

[gcc r15-6303] [PATCH v2 1/2] RISC-V: Document thead-c906, xiangshan-nanhu, and generic-ooo

https://gcc.gnu.org/g:5601c411f4ffdb8bbfec09a58234ab2ebc5de986 commit r15-6303-g5601c411f4ffdb8bbfec09a58234ab2ebc5de986 Author: Anton Blanchard Date: Tue Dec 17 07:30:55 2024 -0700 [PATCH v2 1/2] RISC-V: Document thead-c906, xiangshan-nanhu, and generic-ooo gcc/ChangeLog

[gcc r15-6257] [PATCH v3] match.pd: Add pattern to simplify `(a - 1) & -a` to `0`

https://gcc.gnu.org/g:ad519f46194a7ab1671470a236c67ae17cb98ead commit r15-6257-gad519f46194a7ab1671470a236c67ae17cb98ead Author: Jovan Vukic Date: Sat Dec 14 14:47:35 2024 -0700 [PATCH v3] match.pd: Add pattern to simplify `(a - 1) & -a` to `0` Thank you for the feedback. I have m

[gcc r15-6046] [committed] RISC-V testsuite changes to test clmul expansion of CRCs

https://gcc.gnu.org/g:3537aa694d7d817ac13c3c2908bda45adfb95511 commit r15-6046-g3537aa694d7d817ac13c3c2908bda45adfb95511 Author: Mariam Arutunian Date: Mon Dec 9 07:29:36 2024 -0700 [committed] RISC-V testsuite changes to test clmul expansion of CRCs This testsuite only patch allo

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