[gcc r16-2395] [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md

https://gcc.gnu.org/g:00e1be7b34f8c009938dde2cf9ca4374243a7a9e commit r16-2395-g00e1be7b34f8c009938dde2cf9ca4374243a7a9e Author: Jeff Law Date: Mon Jul 21 15:58:12 2025 -0600 [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md This is a trivial patch to add a few mis

[gcc r16-2361] [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:a0e28fd03f65bb4c76f8eb5ce1e5d56b76897199 commit r16-2361-ga0e28fd03f65bb4c76f8eb5ce1e5d56b76897199 Author: Paul-Antoine Arras Date: Sat Jul 19 08:40:14 2025 -0600 [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100] This pa

[gcc r16-2360] [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p ()

https://gcc.gnu.org/g:7999eb8672c7a5bb6923b1df75dbf29d60637713 commit r16-2360-g7999eb8672c7a5bb6923b1df75dbf29d60637713 Author: Artemiy Volkov Date: Sat Jul 19 08:03:02 2025 -0600 [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p () > A number of folks hav

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

https://gcc.gnu.org/g:f8a92eb289e64c25f5b1d5e72609c9a079c2ae78 commit f8a92eb289e64c25f5b1d5e72609c9a079c2ae78 Author: Pan Li Date: Tue Jul 8 10:46:29 2025 +0800 RISC-V: Disable uint128_t testcase of SAT_MUL when rv32 The rv32 doesn't support __uint128, and then we will have e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

https://gcc.gnu.org/g:6ae24e5065ec89dd2e760be7fd536ed13df1564a commit 6ae24e5065ec89dd2e760be7fd536ed13df1564a Author: Umesh Kalappa Date: Tue Jul 15 10:35:44 2025 -0600 [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Updated the test for rv32 accordingly and no regress fo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for rv32 SAT_MUL from uint64

https://gcc.gnu.org/g:9f3ebf291ef456b06916321b37121302a9c75fbd commit 9f3ebf291ef456b06916321b37121302a9c75fbd Author: Pan Li Date: Fri Jul 11 08:58:31 2025 +0800 RISC-V: Add testcase for rv32 SAT_MUL from uint64 Add the run and asm testcase for rv32 SAT_MUL, widen mul from ui

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISCV: Remove the v extension requirement for sat scalar run test

https://gcc.gnu.org/g:e24b66b97872557cd6838d68b4e248287ebfb415 commit e24b66b97872557cd6838d68b4e248287ebfb415 Author: Pan Li Date: Wed Jul 9 10:40:52 2025 +0800 RISCV: Remove the v extension requirement for sat scalar run test The sat scalar run test should not require the v exte

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Make zero-stride load broadcast a tunable.

https://gcc.gnu.org/g:ee2202e41d5a7527bbbeae9b5e8d56510aed3b57 commit ee2202e41d5a7527bbbeae9b5e8d56510aed3b57 Author: Robin Dapp Date: Thu Jul 10 09:41:48 2025 +0200 RISC-V: Make zero-stride load broadcast a tunable. This patch makes the zero-stride load broadcast idiom dependent

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:8a0241b80551c06210b3157eee2cb337b97c893c commit 8a0241b80551c06210b3157eee2cb337b97c893c Author: Paul-Antoine Arras Date: Mon Jul 14 06:10:44 2025 -0600 [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] This pattern enables

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12

https://gcc.gnu.org/g:64c0c045836d71452f5fbea309b637b99ba8bc32 commit 64c0c045836d71452f5fbea309b637b99ba8bc32 Author: panciyan Date: Thu Jul 10 06:54:26 2025 + RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12 This patch adds testcase for form11 and form12

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Detect new fusions for RISC-V

https://gcc.gnu.org/g:907baff96653a0c513f250de3280eca25060567b commit 907baff96653a0c513f250de3280eca25060567b Author: Daniel Barboza Date: Thu Jul 10 07:28:38 2025 -0600 [RISC-V] Detect new fusions for RISC-V This is primarily Daniel's work... He's chasing things in QEMU & LLVM

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:4ee8f05c7f1085fe5364ebb58f74e2d42523faae commit 4ee8f05c7f1085fe5364ebb58f74e2d42523faae Author: Pan Li Date: Mon Jul 7 11:13:15 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:aeae7c6f03d3f45288ee30344d84d7e131db951c commit aeae7c6f03d3f45288ee30344d84d7e131db951c Author: Pan Li Date: Mon Jul 7 11:17:00 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost

https://gcc.gnu.org/g:374083a73d9a878dc6b626b97fe1fe9c50e521bc commit 374083a73d9a878dc6b626b97fe1fe9c50e521bc Author: Pan Li Date: Mon Jul 7 11:07:11 2025 +0800 RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB

https://gcc.gnu.org/g:decbd287699d9914862c9bb3bd9ea8a933a7174f commit decbd287699d9914862c9bb3bd9ea8a933a7174f Author: Ciyan Pan Date: Wed Jul 9 08:31:25 2025 -0600 [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB This patch adjust test data for unsigned vector SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests

https://gcc.gnu.org/g:7735ae76a1402a569242bfffb2c3ff1aaeb60551 commit 7735ae76a1402a569242bfffb2c3ff1aaeb60551 Author: Paul-Antoine Arras Date: Wed Jul 9 08:36:24 2025 -0600 [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests zvfh is not enabled at the testsuite lev

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector

https://gcc.gnu.org/g:16b14d2666f7fd55c51093b05455f922e816389b commit 16b14d2666f7fd55c51093b05455f922e816389b Author: Jeff Law Date: Wed Jul 9 05:23:34 2025 -0600 [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector AVL propagation currently assumes that it c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Do not use vsetivli for THeadVector.

https://gcc.gnu.org/g:e88c4159232d1f69f5c939e06dd6878b7e5bc472 commit e88c4159232d1f69f5c939e06dd6878b7e5bc472 Author: Robin Dapp Date: Tue Jul 8 11:35:12 2025 +0200 RISC-V: Do not use vsetivli for THeadVector. In emit_vlmax_insn_lra we use a vsetivli for an immediate AVL. XTH

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore non-types in builtin function hash.

https://gcc.gnu.org/g:fbe8a3fda1677ef823772dacd86a1a5e95a47386 commit fbe8a3fda1677ef823772dacd86a1a5e95a47386 Author: Robin Dapp Date: Tue Jul 8 11:17:41 2025 +0200 RISC-V: Ignore non-types in builtin function hash. If a user passes a string that doesn't represent a variable we s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] riscv: allow zero in zacas subword atomic cas

https://gcc.gnu.org/g:07f75a579f31e037a311cfb388c40ef6e70646ad commit 07f75a579f31e037a311cfb388c40ef6e70646ad Author: Andreas Schwab Date: Tue Jul 8 07:32:17 2025 -0600 [PATCH] riscv: allow zero in zacas subword atomic cas gcc: PR target/120995 * config/ri

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed][RISC-V] Fix testsuite fallout from check-function-bodies change

https://gcc.gnu.org/g:045d0c6f9efa44fd6ba4a3a144f0881a0a4de1ad commit 045d0c6f9efa44fd6ba4a3a144f0881a0a4de1ad Author: Jeff Law Date: Mon Jul 7 20:42:04 2025 -0600 [committed][RISC-V] Fix testsuite fallout from check-function-bodies change Minor fallout from HJ's recent change to

[gcc r16-2269] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

https://gcc.gnu.org/g:3fbed69502770851c8a5bfece99e9ee8c6d9e4b0 commit r16-2269-g3fbed69502770851c8a5bfece99e9ee8c6d9e4b0 Author: Umesh Kalappa Date: Tue Jul 15 10:35:44 2025 -0600 [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Updated the test for rv32 accordingly and no

[gcc r15-9973] [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions

https://gcc.gnu.org/g:0588de08620cbe7cbb545ced1e2c470e3a521481 commit r15-9973-g0588de08620cbe7cbb545ced1e2c470e3a521481 Author: Jeff Law Date: Mon Jun 30 14:38:33 2025 -0600 [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions I've gone back

[gcc r15-9970] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:e7d4593d6932c3d16e3cdc837538403859edb52f commit r15-9970-ge7d4593d6932c3d16e3cdc837538403859edb52f Author: Jeff Law Date: Mon Jun 23 18:27:49 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V Fix typo in comment spotted b

[gcc r15-9972] RISC-V: prefetch: fix LRA failing to allocate reg [PR118241]

https://gcc.gnu.org/g:bf6b07491e549af8ca9a27ac04f4d90c41d6a97c commit r15-9972-gbf6b07491e549af8ca9a27ac04f4d90c41d6a97c Author: Vineet Gupta Date: Fri Jul 4 12:33:51 2025 -0700 RISC-V: prefetch: fix LRA failing to allocate reg [PR118241] prefetch was recently fixed/tightened (wit

[gcc r15-9971] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4

https://gcc.gnu.org/g:b5d0cfab39608ff1f010a571122d6105b6e0e91e commit r15-9971-gb5d0cfab39608ff1f010a571122d6105b6e0e91e Author: Vineet Gupta Date: Fri Jul 4 12:33:09 2025 -0700 RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 Spotted this by chance as I saw a simil

[gcc r15-9969] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:4157d433df1ccc30ca2db2e4e9448318d730299f commit r15-9969-g4157d433df1ccc30ca2db2e4e9448318d730299f Author: Jeff Law Date: Sat Jun 21 08:24:58 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V The RISC-V prefetch support i

[gcc r16-2230] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:99a3c71db6edb8dc8c426cb2530f9cefbb5bfc9e commit r16-2230-g99a3c71db6edb8dc8c426cb2530f9cefbb5bfc9e Author: Paul-Antoine Arras Date: Mon Jul 14 06:10:44 2025 -0600 [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] This patter

[gcc r15-9963] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

https://gcc.gnu.org/g:d8f2b4f1781ca02d3f74cc88467f97c2d68b471e commit r15-9963-gd8f2b4f1781ca02d3f74cc88467f97c2d68b471e Author: Alexey Merzlyakov Date: Wed Jul 2 11:29:00 2025 -0600 [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] It corrects the s

[gcc r15-9962] [PATCH] riscv: allow zero in zacas subword atomic cas

https://gcc.gnu.org/g:8f93b00a241a242677a901812f1a12e8960a5dc2 commit r15-9962-g8f93b00a241a242677a901812f1a12e8960a5dc2 Author: Andreas Schwab Date: Tue Jul 8 07:32:17 2025 -0600 [PATCH] riscv: allow zero in zacas subword atomic cas gcc: PR target/120995 *

[gcc r16-2173] [PATCH] libgcc: PR target/116363 Fix SFtype to UDWtype conversion

https://gcc.gnu.org/g:e6f2daff77ee1f709105cb9f8e3e92f04c179431 commit r16-2173-ge6f2daff77ee1f709105cb9f8e3e92f04c179431 Author: Jan Dubiec Date: Thu Jul 10 07:41:08 2025 -0600 [PATCH] libgcc: PR target/116363 Fix SFtype to UDWtype conversion This patch fixes SFtype to UDWtype (ak

[gcc r16-2172] [RISC-V] Detect new fusions for RISC-V

https://gcc.gnu.org/g:742f55622690d35c6cc95f2b8722307699731571 commit r16-2172-g742f55622690d35c6cc95f2b8722307699731571 Author: Daniel Barboza Date: Thu Jul 10 07:28:38 2025 -0600 [RISC-V] Detect new fusions for RISC-V This is primarily Daniel's work... He's chasing things in QE

[gcc r16-2139] [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests

https://gcc.gnu.org/g:f32d34c2b03c55c3ae7cf282e5d2cc24a4d758e4 commit r16-2139-gf32d34c2b03c55c3ae7cf282e5d2cc24a4d758e4 Author: Paul-Antoine Arras Date: Wed Jul 9 08:36:24 2025 -0600 [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests zvfh is not enabled at the tes

[gcc r16-2138] [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB

https://gcc.gnu.org/g:2c5742304ef6dc56e4bebcc10f17822b6dc70ead commit r16-2138-g2c5742304ef6dc56e4bebcc10f17822b6dc70ead Author: Ciyan Pan Date: Wed Jul 9 08:31:25 2025 -0600 [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB This patch adjust test data for unsigned vecto

[gcc r16-2135] [PATCH] [PR target/109286] H8/300: Fix warnings about initfini sections missing attributes

https://gcc.gnu.org/g:2e6dc9e19cdac43354608a1fc29fe31ec614775c commit r16-2135-g2e6dc9e19cdac43354608a1fc29fe31ec614775c Author: Jan Dubiec Date: Wed Jul 9 06:09:20 2025 -0600 [PATCH] [PR target/109286] H8/300: Fix warnings about initfini sections missing attributes The patch cha

[gcc r16-2132] [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector

https://gcc.gnu.org/g:f2e3886a30c771b104bc2714992e072b21a52e76 commit r16-2132-gf2e3886a30c771b104bc2714992e072b21a52e76 Author: Jeff Law Date: Wed Jul 9 05:23:34 2025 -0600 [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector AVL propagation currently assumes

[gcc r16-2099] [PATCH] riscv: allow zero in zacas subword atomic cas

https://gcc.gnu.org/g:3fd638a9e5497dfdf00f1783d6e704af03fb44b0 commit r16-2099-g3fd638a9e5497dfdf00f1783d6e704af03fb44b0 Author: Andreas Schwab Date: Tue Jul 8 07:32:17 2025 -0600 [PATCH] riscv: allow zero in zacas subword atomic cas gcc: PR target/120995 *

[gcc r16-2082] [committed] Minor fix to gcc.dg/torture/pr120654.c

https://gcc.gnu.org/g:477abe67d34f7f8d1b0b12408e08769995b6ca9e commit r16-2082-g477abe67d34f7f8d1b0b12408e08769995b6ca9e Author: Jeff Law Date: Mon Jul 7 20:48:17 2025 -0600 [committed] Minor fix to gcc.dg/torture/pr120654.c I don't recall which port complained, but pr120654.c was

[gcc r16-2081] [committed][RISC-V] Fix testsuite fallout from check-function-bodies change

https://gcc.gnu.org/g:7b1e8e0e85ec6f9d80ceb0d38355b2fcd4785f67 commit r16-2081-g7b1e8e0e85ec6f9d80ceb0d38355b2fcd4785f67 Author: Jeff Law Date: Mon Jul 7 20:42:04 2025 -0600 [committed][RISC-V] Fix testsuite fallout from check-function-bodies change Minor fallout from HJ's recent

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:85ae875672710f92b9d3253bd017cf7516970b9d commit 85ae875672710f92b9d3253bd017cf7516970b9d Author: Pan Li Date: Wed Jul 2 10:52:25 2025 +0800 RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t Add run and tree-optimized check for unsigned scalar

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: prefetch: fix LRA failing to allocate reg [PR118241]

https://gcc.gnu.org/g:46f3e46cf0f5321519a8f690c09e3285595f5a05 commit 46f3e46cf0f5321519a8f690c09e3285595f5a05 Author: Vineet Gupta Date: Fri Jul 4 12:33:51 2025 -0700 RISC-V: prefetch: fix LRA failing to allocate reg [PR118241] prefetch was recently fixed/tightened (with Q reg co

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4

https://gcc.gnu.org/g:ae406c5d93ad230c5861717700ed25ef45b8a999 commit ae406c5d93ad230c5861717700ed25ef45b8a999 Author: Vineet Gupta Date: Fri Jul 4 12:33:09 2025 -0700 RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 Spotted this by chance as I saw a similar fixup i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost

https://gcc.gnu.org/g:b3df1cb98ddf0975d10ba741a61a5d8ea97c339b commit b3df1cb98ddf0975d10ba741a61a5d8ea97c339b Author: Pan Li Date: Thu Jul 3 17:07:44 2025 +0800 RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add basic instrumentation to fusion detection

https://gcc.gnu.org/g:d7f7353440ff3c6856cf1bfb4bb79c86ed4c3efe commit d7f7353440ff3c6856cf1bfb4bb79c86ed4c3efe Author: Shreya Munnangi Date: Thu Jul 3 21:03:03 2025 -0600 [RISC-V] Add basic instrumentation to fusion detection We were looking to evaluate some changes from Artemiy t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2

https://gcc.gnu.org/g:ede8592ee23e90d478ec1a4d516a275ab995225e commit ede8592ee23e90d478ec1a4d516a275ab995225e Author: panciyan Date: Tue Jun 24 09:58:14 2025 +0800 RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2 This patch adds testcase for form2, as shown below:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Implement unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:03d7be4ac9b0f81757ab3cffbf42478d733d5c56 commit 03d7be4ac9b0f81757ab3cffbf42478d733d5c56 Author: Pan Li Date: Wed Jul 2 10:35:10 2025 +0800 RISC-V: Implement unsigned scalar SAT_MUL from uint128_t This patch would like to implement the SAT_MUL scalar unsigned

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:2c8e307289d06a3a59dcf2599d5502f26ab04352 commit 2c8e307289d06a3a59dcf2599d5502f26ab04352 Author: Pan Li Date: Thu Jul 3 17:17:28 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:60e19287795ef881f897b087a5519eec12d56455 commit 60e19287795ef881f897b087a5519eec12d56455 Author: Pan Li Date: Thu Jul 3 17:16:21 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Refactor record_function_versions.

https://gcc.gnu.org/g:7363e569418ebe52a606c6e2078e07b475881ba0 commit 7363e569418ebe52a606c6e2078e07b475881ba0 Author: Alfie Richards Date: Thu Mar 27 14:12:06 2025 + Refactor record_function_versions. Renames record_function_versions to add_function_version, and make it e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates

https://gcc.gnu.org/g:477d40bc7f7a18c70471117c2324e5812b0ab9dc commit 477d40bc7f7a18c70471117c2324e5812b0ab9dc Author: Jeff Law Date: Thu Jul 3 06:44:31 2025 -0600 [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates A number of folks have had their

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

https://gcc.gnu.org/g:7c4170930735d592fa0c4244c3699f129d3910cf commit 7c4170930735d592fa0c4244c3699f129d3910cf Author: Dimitar Dimitrov Date: Fri Jun 20 20:57:15 2025 +0300 RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs Some test cases explicitly set -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

https://gcc.gnu.org/g:09f1fddc57b496abc27eb1a3f0cea96d0e22e388 commit 09f1fddc57b496abc27eb1a3f0cea96d0e22e388 Author: Alexey Merzlyakov Date: Wed Jul 2 11:29:00 2025 -0600 [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] It corrects the shift type

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions

https://gcc.gnu.org/g:102e91566d6f90ecd52f50c4a340d116dc8b1f1a commit 102e91566d6f90ecd52f50c4a340d116dc8b1f1a Author: Jeff Law Date: Mon Jun 30 14:38:33 2025 -0600 [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions I've gone back and forth

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Correct CFA notes for stack-clash protection [PR120714]

https://gcc.gnu.org/g:76d99d9eb3a5830d0865ca27fa52644479c0e5a0 commit 76d99d9eb3a5830d0865ca27fa52644479c0e5a0 Author: Alexey Merzlyakov Date: Mon Jun 30 13:58:29 2025 -0600 [RISC-V] Correct CFA notes for stack-clash protection [PR120714] Fixes incorrect SP-addresses used in CFA n

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:c20878bc23d6b251877d0c9526f411f88ab5acec commit c20878bc23d6b251877d0c9526f411f88ab5acec Author: Pan Li Date: Fri Jun 27 09:09:08 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:de5e9aa67d08dcdd0114608bc50097e3b4d54d91 commit de5e9aa67d08dcdd0114608bc50097e3b4d54d91 Author: Pan Li Date: Fri Jun 27 09:06:38 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test due to cost model change

https://gcc.gnu.org/g:927d0cb43e27a0639ef0fd1a0115918da6894459 commit 927d0cb43e27a0639ef0fd1a0115918da6894459 Author: Pan Li Date: Fri Jun 27 11:35:18 2025 +0800 RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cost of vx to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

https://gcc.gnu.org/g:f6f8088e9b30bfba11fb570a540794173bf0c27b commit f6f8088e9b30bfba11fb570a540794173bf0c27b Author: Pan Li Date: Fri Jun 27 09:02:03 2025 +0800 RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore -Oz for most rvv testcase [NFC]

https://gcc.gnu.org/g:4c823d938d2c8d1dd66871da31d15ffe4265a8bc commit 4c823d938d2c8d1dd66871da31d15ffe4265a8bc Author: Kito Cheng Date: Mon Jun 30 14:18:07 2025 +0800 RISC-V: Ignore -Oz for most rvv testcase [NFC] Most testcase in rvv folder already ignore -Oz, but some of them

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Primary vector pipeline model for sifive 7 series

https://gcc.gnu.org/g:13b49dd649ba46de1ca5731c7a5dcfe759f6f6e2 commit 13b49dd649ba46de1ca5731c7a5dcfe759f6f6e2 Author: Kito Cheng Date: Thu Jun 19 14:31:42 2025 +0800 RISC-V: Primary vector pipeline model for sifive 7 series This commit introduces a primary vector pipeline model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659

https://gcc.gnu.org/g:71cc3ca6ac57deb06a999e209653c5db913b8037 commit 71cc3ca6ac57deb06a999e209653c5db913b8037 Author: Kito Cheng Date: Tue Jun 17 16:20:19 2025 +0800 RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659] gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:0be8dc16fba358c197b312b836a135cf75b9020c commit 0be8dc16fba358c197b312b836a135cf75b9020c Author: Paul-Antoine Arras Date: Thu Jun 26 13:20:49 2025 + RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pa

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the function bitmap_union_of_preds_with_entry

https://gcc.gnu.org/g:6ce0821aa5ad174979d5fc15db606810b644c8eb commit 6ce0821aa5ad174979d5fc15db606810b644c8eb Author: Jin Ma Date: Sat Jun 28 19:55:00 2025 +0800 RISC-V: Refactor the function bitmap_union_of_preds_with_entry The current implementation of this function is somewhat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pipeline-checker script

https://gcc.gnu.org/g:101b601931434bdce9719b871feb85a1597b0292 commit 101b601931434bdce9719b871feb85a1597b0292 Author: Kito Cheng Date: Thu Jun 26 17:21:27 2025 +0800 RISC-V: Add pipeline-checker script Pipeline checker utility for RISC-V architecture that validates processor

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [sanitizer_common] Fix build on ppc64+musl (#120036)

https://gcc.gnu.org/g:822bd8f017e685471178fb1a2c8b21c2a0d642d8 commit 822bd8f017e685471178fb1a2c8b21c2a0d642d8 Author: Jeff Law Date: Fri Jun 27 15:11:41 2025 -0600 [sanitizer_common] Fix build on ppc64+musl (#120036) Cherry picked from LLVM commit 801b519dfd01e21da0be17aa8f8dc2ce

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking

https://gcc.gnu.org/g:5ad1aa3f754e62d023f75bb0ec2037f5cdab1448 commit 5ad1aa3f754e62d023f75bb0ec2037f5cdab1448 Author: Jeff Law Date: Fri Jun 27 07:00:15 2025 -0600 [RISC-V][PR target/119971] Avoid losing shift count masking Fix typo spotted by Bernhard Reutner-Fischer.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828]

https://gcc.gnu.org/g:058acd7e8508ec11d4c17c8778912aba63498c4a commit 058acd7e8508ec11d4c17c8778912aba63498c4a Author: Paul-Antoine Arras Date: Wed Jun 25 16:42:00 2025 + RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828] This is a followup to 92e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix build issue

https://gcc.gnu.org/g:14c1c415325a2aa960e350a33fac5dd2eecdb153 commit 14c1c415325a2aa960e350a33fac5dd2eecdb153 Author: Kito Cheng Date: Thu Jun 26 14:35:47 2025 +0800 RISC-V: Fix build issue Apparently I forgot to squash this fix into the previous commit before I push...

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add comment and reorder the the include files in riscv.md [NFC]

https://gcc.gnu.org/g:329a20b72a12c9a1d6524c419371172eb7e96849 commit 329a20b72a12c9a1d6524c419371172eb7e96849 Author: Kito Cheng Date: Thu Jun 26 14:26:57 2025 +0800 RISC-V: Add comment and reorder the the include files in riscv.md [NFC] This patch adds a comment to the riscv.md

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Profiles RVA/B23S64 support.

https://gcc.gnu.org/g:30bc81d98baf775d237d08068e82f065633404dd commit 30bc81d98baf775d237d08068e82f065633404dd Author: Jiawei Date: Tue Jun 24 17:34:05 2025 +0800 RISC-V: Add Profiles RVA/B23S64 support. This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:7579e0cd3b61be067c823f1cea87bbefb5fb9d6f commit 7579e0cd3b61be067c823f1cea87bbefb5fb9d6f Author: Paul-Antoine Arras Date: Tue Jun 24 15:42:50 2025 -0600 RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100] This pattern enables the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:a0cca3923d6233d373e4ab2b56fff5c674dd9224 commit a0cca3923d6233d373e4ab2b56fff5c674dd9224 Author: Jeff Law Date: Mon Jun 23 18:27:49 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V Fix typo in comment spotted by Peter B.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:0378e1e4efed98f9c6e111e2e63b546c7c66979c commit 0378e1e4efed98f9c6e111e2e63b546c7c66979c Author: Pan Li Date: Sat Jun 21 10:07:38 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:26cde1e545b49f7a4bc2a1c5b46198c087be828c commit 26cde1e545b49f7a4bc2a1c5b46198c087be828c Author: Pan Li Date: Sat Jun 21 09:10:07 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

https://gcc.gnu.org/g:28a7e66cafd789919225b440b38e85bc4cf1d048 commit 28a7e66cafd789919225b440b38e85bc4cf1d048 Author: Pan Li Date: Sat Jun 21 09:00:16 2025 +0800 RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts

https://gcc.gnu.org/g:5ccee5646b67e249d44d38a67b36b2bff6129ef3 commit 5ccee5646b67e249d44d38a67b36b2bff6129ef3 Author: Andrew Pinski Date: Sun Jun 22 12:35:19 2025 -0600 [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts So this is Andrew's patch from the PR. We weren't

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:30e7306b74952c673517e5f686faeb8afce8395d commit 30e7306b74952c673517e5f686faeb8afce8395d Author: Jeff Law Date: Sat Jun 21 08:24:58 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V The RISC-V prefetch support is broken i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for expand_select_vldi [PR120652]

https://gcc.gnu.org/g:6c397a7977e26f19757ed1182994af2cfdc3d22f commit 6c397a7977e26f19757ed1182994af2cfdc3d22f Author: Pan Li Date: Thu Jun 19 18:58:17 2025 +0800 RISC-V: Fix ICE for expand_select_vldi [PR120652] The will be one ICE when expand pass, the bt similar as below.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Force several tests to use rocket tuning

https://gcc.gnu.org/g:4431d2438c05ae2e1c54eb0e6ae4a35c744dc20a commit 4431d2438c05ae2e1c54eb0e6ae4a35c744dc20a Author: Jeff Law Date: Thu Jun 19 20:58:56 2025 -0600 [RISC-V] Force several tests to use rocket tuning My tester has been flagging these regressions since the default co

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used

https://gcc.gnu.org/g:2ea35c173f5af1599ead63b05eeec1e317fef7bd commit 2ea35c173f5af1599ead63b05eeec1e317fef7bd Author: Sosutha Sethuramapandian Date: Thu Jun 19 20:53:56 2025 -0600 [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used longl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:7ec437266df8d719d18f5ddc60ef5207b479cdbc commit 7ec437266df8d719d18f5ddc60ef5207b479cdbc Author: Pan Li Date: Thu Jun 19 10:49:07 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:1b7fcb4495f2d6dcf999f92781c21ccc2d1b58a0 commit 1b7fcb4495f2d6dcf999f92781c21ccc2d1b58a0 Author: Pan Li Date: Thu Jun 19 10:47:33 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost

https://gcc.gnu.org/g:34c5807cee5a608e4321facb1ae5f8badd012c83 commit 34c5807cee5a608e4321facb1ae5f8badd012c83 Author: Pan Li Date: Thu Jun 19 10:44:14 2025 +0800 RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add generic tune as default.

https://gcc.gnu.org/g:d2b21c2620e40d2da95a8538c799c278843dff60 commit d2b21c2620e40d2da95a8538c799c278843dff60 Author: Dongyan Chen Date: Wed Jun 18 19:47:28 2025 +0800 RISC-V: Add generic tune as default. According to the discussion in https://gcc.gnu.org/pipermail/gcc-patche

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv_2x_xlen_mode_p [NFC]

https://gcc.gnu.org/g:3becefcb2e74d5047a15e81563421368a9b03ad0 commit 3becefcb2e74d5047a15e81563421368a9b03ad0 Author: Kito Cheng Date: Tue Jun 17 13:01:01 2025 +0800 RISC-V: Use riscv_2x_xlen_mode_p [NFC] Use riscv_v_ext_mode_p to check the mode size is 2x XLEN, instead of us

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding cost model for zilsd

https://gcc.gnu.org/g:f4beb3460b90efefade6daf5c50cf74633b2ce19 commit f4beb3460b90efefade6daf5c50cf74633b2ce19 Author: Kito Cheng Date: Tue Jun 17 12:56:17 2025 +0800 RISC-V: Adding cost model for zilsd Motivation of this patch is we want to use ld/sd if possible when zilsd is

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:16a379bb686a4debb877b8cd5598381959183727 commit 16a379bb686a4debb877b8cd5598381959183727 Author: Pan Li Date: Tue Jun 17 10:08:44 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:7ad53e8abcaebe37bb355079d5c4d83ce34d4fcd commit 7ad53e8abcaebe37bb355079d5c4d83ce34d4fcd Author: Pan Li Date: Tue Jun 17 10:05:33 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost

https://gcc.gnu.org/g:b7ccbdc0d5a272597271d88ec3176e0ab11f9fcf commit b7ccbdc0d5a272597271d88ec3176e0ab11f9fcf Author: Pan Li Date: Tue Jun 17 10:00:54 2025 +0800 RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v1] RISC-V: Use scratch reg for loop control

https://gcc.gnu.org/g:a97eb08ac396591338b40f81be27ead5a498a1be commit a97eb08ac396591338b40f81be27ead5a498a1be Author: Umesh Kalappa Date: Tue Jun 17 07:23:41 2025 -0600 [PATCH v1] RISC-V: Use scratch reg for loop control By using the scratch register for loop control rather than

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add -fno-pie flags to testcases

https://gcc.gnu.org/g:9fe9f65082c770a91775131ffc69b2ecf47cd9e4 commit 9fe9f65082c770a91775131ffc69b2ecf47cd9e4 Author: Kito Cheng Date: Tue Jun 17 12:52:00 2025 +0800 RISC-V: Add -fno-pie flags to testcases PIE may cause some code gen difference in the testcases, that will cause

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine VX combine test case 0 to avoid code duplication

https://gcc.gnu.org/g:5abb21b4d9c59c735355ac0abd4dd05cf441038d commit 5abb21b4d9c59c735355ac0abd4dd05cf441038d Author: Pan Li Date: Sun Jun 15 16:28:38 2025 +0800 RISC-V: Refine VX combine test case 0 to avoid code duplication The case 0 for vx combine def functions are most the s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Profiles string in RV23.

https://gcc.gnu.org/g:9f15440c022ca9a0266445a665f7e07415817d10 commit 9f15440c022ca9a0266445a665f7e07415817d10 Author: Jiawei Date: Mon Jun 16 11:21:29 2025 +0800 RISC-V: Update Profiles string in RV23. Add b-ext in RVA/B23 as independent extension flags and add supm in RVA23.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:05bc63f38afa102e6766d9abb52db3174a4e4153 commit 05bc63f38afa102e6766d9abb52db3174a4e4153 Author: Pan Li Date: Sat Jun 14 22:34:36 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:a0d1d0c39fd5d9f54ec94a94dc05fa41ddeef0fd commit a0d1d0c39fd5d9f54ec94a94dc05fa41ddeef0fd Author: Pan Li Date: Sat Jun 14 22:32:23 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

https://gcc.gnu.org/g:4af1a958a3d8a413e3b01a1bfe2d493db3ec1e69 commit 4af1a958a3d8a413e3b01a1bfe2d493db3ec1e69 Author: Pan Li Date: Sat Jun 14 22:29:40 2025 +0800 RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:31baabf7b56938c96dbc6b68781c7da932d76706 commit 31baabf7b56938c96dbc6b68781c7da932d76706 Author: Pan Li Date: Thu Jun 12 10:42:39 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:0363f535e1721362c539bc1462bd7296110c4f15 commit 0363f535e1721362c539bc1462bd7296110c4f15 Author: Pan Li Date: Thu Jun 12 10:23:49 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b0d572cc865bafacf07569608a47702158f0e4b6 commit b0d572cc865bafacf07569608a47702158f0e4b6 Author: Pan Li Date: Thu Jun 12 09:12:09 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:308422b0ad1d1afe26dec32267bcb16717e7956a commit 308422b0ad1d1afe26dec32267bcb16717e7956a Author: Pan Li Date: Wed Jun 11 21:51:08 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15 Add asm dump check t

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