[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:c81295d19cb5c0d9f92369d5a66aa07652d20c79 commit c81295d19cb5c0d9f92369d5a66aa07652d20c79 Author: Pan Li Date: Wed May 28 16:22:04 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:16eca418d548700f84a5a99bfb224af9824c4b59 commit 16eca418d548700f84a5a99bfb224af9824c4b59 Author: Pan Li Date: Tue May 20 15:06:34 2025 +0800 RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Smrnmi extension.

https://gcc.gnu.org/g:11d80e3207f54627e5ec6520bfb26df72e71c2ed commit 11d80e3207f54627e5ec6520bfb26df72e71c2ed Author: Jiawei Date: Thu Jun 5 11:24:43 2025 +0800 RISC-V: Support Smrnmi extension. Support the Smrnmi extension, which provides new CSRs for Machine mode Non-Maskab

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Clear high or low bits using shift pairs

https://gcc.gnu.org/g:634a4be733537d950431a303a46c3c8bd5fea629 commit 634a4be733537d950431a303a46c3c8bd5fea629 Author: Shreya Munnangi Date: Wed May 21 18:49:14 2025 -0600 [RISC-V] Clear high or low bits using shift pairs So the first special case of clearing bits from Shreya's wo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

https://gcc.gnu.org/g:29c38bf92aaf91ab6ca9ec05cbad4833a60fa15e commit 29c38bf92aaf91ab6ca9ec05cbad4833a60fa15e Author: Pan Li Date: Thu Jun 5 11:04:33 2025 +0800 RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv The div of rvv has not such insn v2 = div (vec_dup (x), v1),

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Implement full-featured iterator for riscv_subset_list [NFC]

https://gcc.gnu.org/g:d581dfe39daff4ddc2cff49445f6e78030076c69 commit d581dfe39daff4ddc2cff49445f6e78030076c69 Author: Kito Cheng Date: Mon May 26 14:43:47 2025 +0800 RISC-V: Implement full-featured iterator for riscv_subset_list [NFC] This commit implements a full-featured iterat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve (x << C1) + C2 split code

https://gcc.gnu.org/g:f7e1e41c2525aca1f0c876e872032b08bccb9d18 commit f7e1e41c2525aca1f0c876e872032b08bccb9d18 Author: Jeff Law Date: Wed May 21 16:04:58 2025 -0600 [RISC-V] Improve (x << C1) + C2 split code I wrote this a couple months ago to fix an instruction count regression i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Don't use structured binding in riscv-common.cc

https://gcc.gnu.org/g:2b2971fd70d9415ed8f6ce00b1919f7da9acbce2 commit 2b2971fd70d9415ed8f6ce00b1919f7da9acbce2 Author: Kito Cheng Date: Thu Jun 5 15:23:59 2025 +0800 RISC-V: Don't use structured binding in riscv-common.cc It's new C++ language feature introduced in C++17, which is

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve sequences to generate -1, 1 in some cases.

https://gcc.gnu.org/g:4a89441e769a800b3e8d1a9150a36dd620247730 commit 4a89441e769a800b3e8d1a9150a36dd620247730 Author: Jeff Law Date: Thu Jun 5 06:17:25 2025 -0600 [RISC-V] Improve sequences to generate -1, 1 in some cases. This patch has a minor improvement to if-converted sequen

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sstvecd extension.

https://gcc.gnu.org/g:7d138118ccd9a16e8800f8c89a01b273fc105c9d commit 7d138118ccd9a16e8800f8c89a01b273fc105c9d Author: Jiawei Date: Thu Jun 5 13:52:08 2025 +0800 RISC-V: Support Sstvecd extension. Support the Sstvecd extension, which allows Supervisor Trap Vector Base Address

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Ssu64xl extension.

https://gcc.gnu.org/g:1787f1a3fdcded7bb47d6970ea828e597543eae6 commit 1787f1a3fdcded7bb47d6970ea828e597543eae6 Author: Jiawei Date: Thu Jun 5 13:59:14 2025 +0800 RISC-V: Support Ssu64xl extension. Support the Ssu64xl extension, which requires UXLEN to be 64. gcc/ChangeLog

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sstvala extension.

https://gcc.gnu.org/g:7eb7f4fab1c4713daeca44af509c55aec5232b24 commit 7eb7f4fab1c4713daeca44af509c55aec5232b24 Author: Jiawei Date: Thu Jun 5 13:46:39 2025 +0800 RISC-V: Support Sstvala extension. Support the Sstvala extension, which provides all needed values in Supervisor Tr

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sscounterenw extension.

https://gcc.gnu.org/g:f17303cc246ec9887b0e97619783c0f5fb03ac40 commit f17303cc246ec9887b0e97619783c0f5fb03ac40 Author: Jiawei Date: Thu Jun 5 13:33:21 2025 +0800 RISC-V: Support Sscounterenw extension. Support the Sscounterenw extension, which allows writeable enables for any

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Ssccptr extension.

https://gcc.gnu.org/g:f58bec28867f6e555ef53b64b1a7dd31b61e64cb commit f58bec28867f6e555ef53b64b1a7dd31b61e64cb Author: Jiawei Date: Thu Jun 5 13:15:02 2025 +0800 RISC-V: Support Ssccptr extension. Support the Ssccptr extension, which allows the main memory to support page tabl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sm/scsrind extensions.

https://gcc.gnu.org/g:d9b60c3b9ff4bfa0de2c800e2fd98bd4c3df5c8f commit d9b60c3b9ff4bfa0de2c800e2fd98bd4c3df5c8f Author: Jiawei Date: Thu Jun 5 10:16:19 2025 +0800 RISC-V: Support Sm/scsrind extensions. Support the Sm/scsrind extensions, which provide indirect access to machine-

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update extension defination.

https://gcc.gnu.org/g:3ba8b08ac7bed98b1aea6292b5b1cc2b8d05d11e commit 3ba8b08ac7bed98b1aea6292b5b1cc2b8d05d11e Author: Jiawei Date: Thu Jun 5 09:38:40 2025 +0800 RISC-V: Update extension defination. Update the defination of RISC-V extensions in riscv-ext.def. gcc/ChangeLo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.

https://gcc.gnu.org/g:1253ab87ca9ffb55c708be9891c105e4992945b0 commit 1253ab87ca9ffb55c708be9891c105e4992945b0 Author: Dongyan Chen Date: Wed Jun 4 08:03:31 2025 -0600 [PATCH] RISC-V: Imply zicsr for svade and svadu extensions. This patch implies zicsr for svade and svadu extensio

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Add svbare extension.

https://gcc.gnu.org/g:bed8b673f96ad1225dd33578c744dfc1b2a8a2a7 commit bed8b673f96ad1225dd33578c744dfc1b2a8a2a7 Author: Dongyan Chen Date: Wed Jun 4 07:57:01 2025 -0600 [PATCH v2] RISC-V: Add svbare extension. This patch support svbare extension, which is an extension in RVA23 prof

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC]

https://gcc.gnu.org/g:90c842426e9fe9ce043d351d62888cf9299cf4b6 commit 90c842426e9fe9ce043d351d62888cf9299cf4b6 Author: Pan Li Date: Wed Jun 4 11:06:52 2025 +0800 RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC] Some similar code could be wrapped to func get_vect

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Shlcofideleg extension.

https://gcc.gnu.org/g:087e777ec59f06f2d67db83d2f7bb984dc616642 commit 087e777ec59f06f2d67db83d2f7bb984dc616642 Author: Jiawei Date: Tue May 27 14:37:03 2025 +0800 RISC-V: Add Shlcofideleg extension. This patch add the RISC-V Shlcofideleg extension. It supports delegating LCOFI

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vdiv.vx combine

https://gcc.gnu.org/g:6f86911ab7ea1310d1b14dc495d9a3d1385b90f6 commit 6f86911ab7ea1310d1b14dc495d9a3d1385b90f6 Author: Pan Li Date: Mon Jun 2 21:21:18 2025 +0800 RISC-V: Reconcile the existing test for vdiv.vx combine Some existing vdiv related test need some adjust for the as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:a1bc833b543a208568c8b13de7e2180b6daca172 commit a1bc833b543a208568c8b13de7e2180b6daca172 Author: Pan Li Date: Mon Jun 2 17:03:02 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for vec

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:dcf0e76c9b674794f39ebaa0a5b9630ddff5fb90 commit dcf0e76c9b674794f39ebaa0a5b9630ddff5fb90 Author: Pan Li Date: Mon Jun 2 17:01:27 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use helper function to get FPR to VR move cost

https://gcc.gnu.org/g:03d5c7af1264b432eb19c317d19474fa5b0a7acc commit 03d5c7af1264b432eb19c317d19474fa5b0a7acc Author: Paul-Antoine Arras Date: Wed May 28 12:09:22 2025 +0200 RISC-V: Use helper function to get FPR to VR move cost Since last patch introduced get_fr2vr_cost () to ge

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost

https://gcc.gnu.org/g:a16aae22d395fa90f59a781b2911e40793c36b88 commit a16aae22d395fa90f59a781b2911e40793c36b88 Author: Pan Li Date: Mon Jun 2 16:56:59 2025 +0800 RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost This patch would like to combine the vec_duplicate + v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100]

https://gcc.gnu.org/g:f7a94e59a0ec73e18369e419d6b06b945f567d26 commit f7a94e59a0ec73e18369e419d6b06b945f567d26 Author: Paul-Antoine Arras Date: Mon May 12 14:42:24 2025 +0200 RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100] This pattern enables the combine pass (o

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add smcntrpmf extension.

https://gcc.gnu.org/g:e313f013a7ae2b4170a523dae073a36b8f44 commit e313f013a7ae2b4170a523dae073a36b8f44 Author: Dongyan Chen Date: Mon Jun 2 13:30:29 2025 -0600 [PATCH] RISC-V: Add smcntrpmf extension. This patch support smcntrpmf extension[1]. To enable GCC to recogniz

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-riscv-ext-texi

https://gcc.gnu.org/g:21fad71c1c970d1e8eb836ddbca362f4677e3f8b commit 21fad71c1c970d1e8eb836ddbca362f4677e3f8b Author: Kito Cheng Date: Wed May 28 17:59:11 2025 +0800 RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-riscv-ext-texi Separate the build rules to compile and lin

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage vaadd.vv for signed standard name avg_ceil

https://gcc.gnu.org/g:7926027528608ef250b5fd74de8f25d4d87b027b commit 7926027528608ef250b5fd74de8f25d4d87b027b Author: Pan Li Date: Thu May 29 21:19:36 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_ceil The avg_ceil has the rounding mode towards +inf, while the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mode.c

https://gcc.gnu.org/g:cf48dab050510a0f23765c1267fee325d788981b commit cf48dab050510a0f23765c1267fee325d788981b Author: Liao Shihua Date: Sun Jun 1 21:11:25 2025 -0600 [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mode.c This patch fixes the typo in the test case `param-

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for avg_ceil vaadd implementation

https://gcc.gnu.org/g:00da44fa14ebf501fbdd3041ae1fcab891ecc12d commit 00da44fa14ebf501fbdd3041ae1fcab891ecc12d Author: Pan Li Date: Thu May 29 21:33:44 2025 +0800 RISC-V: Add test cases for avg_ceil vaadd implementation Add asm and run testcase for avg_ceil vaadd implementation.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix line too long format issue for autovect.md [NFC]

https://gcc.gnu.org/g:f501c35b983949400843f99c259ad11b11d98a00 commit f501c35b983949400843f99c259ad11b11d98a00 Author: Pan Li Date: Sat May 31 11:01:06 2025 +0800 RISC-V: Fix line too long format issue for autovect.md [NFC] Inspired by the avg_ceil patches, notice there were even

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for avg_ceil

https://gcc.gnu.org/g:580b98e1d79589ccfa01121680ac127e895798fe commit 580b98e1d79589ccfa01121680ac127e895798fe Author: Pan Li Date: Thu May 29 21:31:54 2025 +0800 RISC-V: Reconcile the existing test for avg_ceil Some existing avg_floor test need updated due to change to levera

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add minimal support of double trap extension 1.0

https://gcc.gnu.org/g:ae57b36ec4490523ccacb499aa8c240346e6c39a commit ae57b36ec4490523ccacb499aa8c240346e6c39a Author: Jerry Zhang Jian Date: Wed May 28 10:17:36 2025 +0800 RISC-V: Add minimal support of double trap extension 1.0 Add support of double trap extension [1], enabling

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost

https://gcc.gnu.org/g:87b360b889a83b5cf6c535e77e16e5ccb0ea8b0f commit 87b360b889a83b5cf6c535e77e16e5ccb0ea8b0f Author: Pan Li Date: Wed May 28 16:16:49 2025 +0800 RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:1a15db2f74c66f090f2f405450b6544ef5d1c15e commit 1a15db2f74c66f090f2f405450b6544ef5d1c15e Author: Pan Li Date: Wed May 28 16:20:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid division by zero in check_builtin_call [PR120436].

https://gcc.gnu.org/g:ef85803670709d2175ea5dd59683f3f8586e8299 commit ef85803670709d2175ea5dd59683f3f8586e8299 Author: Robin Dapp Date: Mon May 26 16:16:36 2025 +0200 RISC-V: Avoid division by zero in check_builtin_call [PR120436]. In check_builtin_call we eventually perform a div

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for avg_floor vaadd implementation

https://gcc.gnu.org/g:9f09bc511db814ba928a495995ea44efae3a15cf commit 9f09bc511db814ba928a495995ea44efae3a15cf Author: Pan Li Date: Tue May 27 10:27:01 2025 +0800 RISC-V: Add test cases for avg_floor vaadd implementation Add asm and run testcase for avg_floor vaadd implementation.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for avg_floor

https://gcc.gnu.org/g:474b25ded43f69251b2a1ce23b1d375c0e3cb46c commit 474b25ded43f69251b2a1ce23b1d375c0e3cb46c Author: Pan Li Date: Tue May 27 10:24:56 2025 +0800 RISC-V: Reconcile the existing test for avg_floor Some existing avg_floor test need updated due to change to lever

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage vaadd.vv for signed standard name avg_floor

https://gcc.gnu.org/g:85805f10c0e00165e559cf834236718570649a60 commit 85805f10c0e00165e559cf834236718570649a60 Author: Pan Li Date: Tue May 27 09:53:56 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_floor The signed avg_floor totally match the sematics of fixed

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add andi+bclr synthesis

https://gcc.gnu.org/g:6bece8413ef4fa261d45447d262562f57260b0c5 commit 6bece8413ef4fa261d45447d262562f57260b0c5 Author: Shreya Munnangi Date: Tue May 27 06:43:29 2025 -0600 [RISC-V] Add andi+bclr synthesis So this patch from Shreya adds the ability to use andi + a series of bclr i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:2112e84154c3d9ea77b9ba01b191127fc7fb2754 commit 2112e84154c3d9ea77b9ba01b191127fc7fb2754 Author: Pan Li Date: Sun May 25 17:17:34 2025 +0800 RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.

https://gcc.gnu.org/g:3e7ab4752c4d8c2ea4b23c33639895b0e2e2ec6a commit 3e7ab4752c4d8c2ea4b23c33639895b0e2e2ec6a Author: xuli Date: Fri Dec 27 07:59:31 2024 + RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1. This patch adds testcase for form1, as shown below:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed vector SAT_ADD IMM form 1

https://gcc.gnu.org/g:c97e4137dd1e50420faf90e86b9745cd4603ab32 commit c97e4137dd1e50420faf90e86b9745cd4603ab32 Author: xuli Date: Thu Dec 26 09:39:08 2024 + RISC-V: Add testcases for signed vector SAT_ADD IMM form 1 This patch adds testcase for form1, as shown below:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:6cee635f8075fb7285f3bbc00a1e8fc43f77bac5 commit 6cee635f8075fb7285f3bbc00a1e8fc43f77bac5 Author: Pan Li Date: Sun May 25 17:16:09 2025 +0800 RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost

https://gcc.gnu.org/g:9b0d303b9d02e149d4438001d2eff96d2c077b33 commit 9b0d303b9d02e149d4438001d2eff96d2c077b33 Author: Pan Li Date: Sun May 25 17:13:09 2025 +0800 RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] shift+and+shift for logical and synthesis

https://gcc.gnu.org/g:b2e7fd2c4fa3a8a094d03d71cdb2526f2a2dcbff commit b2e7fd2c4fa3a8a094d03d71cdb2526f2a2dcbff Author: Shreya Munnangi Date: Sat May 24 13:52:55 2025 -0600 [RISC-V] shift+and+shift for logical and synthesis The next chunk of Shreya's work. For this expansi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:aba64354a5abf4a965d85c4150c4ecbfd6c16066 commit aba64354a5abf4a965d85c4150c4ecbfd6c16066 Author: Pan Li Date: Fri May 23 13:29:32 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for vec

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support CPUs in -march.

https://gcc.gnu.org/g:736bdd7569f4775e19e1256ac6bb565636f93dee commit 736bdd7569f4775e19e1256ac6bb565636f93dee Author: Robin Dapp Date: Thu May 8 09:51:45 2025 +0200 RISC-V: Support CPUs in -march. This patch allows an -march string like -march=sifive-p670 in o

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:cfb49a118d73915be9551550b3fd00ba0f622a93 commit cfb49a118d73915be9551550b3fd00ba0f622a93 Author: Pan Li Date: Fri May 23 13:26:41 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost

https://gcc.gnu.org/g:be69c3922f6b95d2b263469d62b3135f2f090d8b commit be69c3922f6b95d2b263469d62b3135f2f090d8b Author: Pan Li Date: Fri May 23 13:22:35 2025 +0800 RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost This patch would like to combine the vec_duplicate + vo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Default-initialize variable.

https://gcc.gnu.org/g:cb1ec115f13d037bcc84c2d58862e9b946e0a3ac commit cb1ec115f13d037bcc84c2d58862e9b946e0a3ac Author: Robin Dapp Date: Thu May 8 10:17:26 2025 +0200 RISC-V: Default-initialize variable. This patch initializes saved_vxrm_mode to VXRM_MODE_NONE. This is a warni

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add autovec mode param.

https://gcc.gnu.org/g:15cc995ae507e4a5f8ace9e9cb6941943ddc2153 commit 15cc995ae507e4a5f8ace9e9cb6941943ddc2153 Author: Robin Dapp Date: Wed May 7 21:02:21 2025 +0200 RISC-V: Add autovec mode param. This patch adds a --param=autovec-mode=. When the param is specified we make a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix some dynamic LMUL costing.

https://gcc.gnu.org/g:0e627a67f17ff9f94c698b6db78111d5da063a5c commit 0e627a67f17ff9f94c698b6db78111d5da063a5c Author: Robin Dapp Date: Fri Feb 7 15:42:28 2025 +0100 RISC-V: Fix some dynamic LMUL costing. With all-SLP we annotate statements slightly differently. This patch us

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

https://gcc.gnu.org/g:2828c84e635ebdfbb942adacabed1737c4b19cc2 commit 2828c84e635ebdfbb942adacabed1737c4b19cc2 Author: Siarhei Volkau Date: Thu May 22 08:52:17 2025 -0600 [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32 Patch is originally from Siarhei Volkau .

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Clear both upper and lower bits using 3 shifts

https://gcc.gnu.org/g:129a47471f7743101b9bf5470679bcb9f0641e3f commit 129a47471f7743101b9bf5470679bcb9f0641e3f Author: Shreya Munnangi Date: Thu May 22 11:51:01 2025 -0600 [RISC-V] Clear both upper and lower bits using 3 shifts So the next step in Shreya's work. In the prior patc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.

https://gcc.gnu.org/g:a02a5bc24013f9e05f1c514ad37ec6aa67947cc0 commit a02a5bc24013f9e05f1c514ad37ec6aa67947cc0 Author: Dongyan Chen Date: Wed May 21 21:46:52 2025 -0600 [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level. Failed testcases occurr

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:80459040aadce5e2e87b113aee7fad6185c14e51 commit 80459040aadce5e2e87b113aee7fad6185c14e51 Author: Pan Li Date: Tue May 20 22:30:04 2025 +0800 RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost

https://gcc.gnu.org/g:726454e4d06d107605d3d34fe4a2f9bc1a2a1a99 commit 726454e4d06d107605d3d34fe4a2f9bc1a2a1a99 Author: Pan Li Date: Tue May 20 15:00:15 2025 +0800 RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost This patch would like to combine the vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120368] Fix 32bit shift on rv64

https://gcc.gnu.org/g:1384d5ed1a80d2089bd7d13815e401c26cf26c9a commit 1384d5ed1a80d2089bd7d13815e401c26cf26c9a Author: Jeff Law Date: Wed May 21 14:15:23 2025 -0600 [RISC-V][PR target/120368] Fix 32bit shift on rv64 So a followup to last week's bugfix. In last week's change we we

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the sa

https://gcc.gnu.org/g:78a47aa5682375680a612b363beb5aa24f5d4860 commit 78a47aa5682375680a612b363beb5aa24f5d4860 Author: Umesh Kalappa Date: Tue May 20 11:57:00 2025 -0600 [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same. The RI

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Infrastructure of synthesizing logical AND with constant

https://gcc.gnu.org/g:4787ad29a5421b607e535beb749ad3344748c477 commit 4787ad29a5421b607e535beb749ad3344748c477 Author: Shreya Munnangi Date: Tue May 20 20:15:42 2025 -0600 [RISC-V] Infrastructure of synthesizing logical AND with constant So this is the next step on the path to mvc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performanc

https://gcc.gnu.org/g:208a74e05db9a2d9e2558f1dea92d15d69243ff8 commit 208a74e05db9a2d9e2558f1dea92d15d69243ff8 Author: Umesh Kalappa Date: Tue May 20 11:50:46 2025 -0600 [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MI

[gcc r16-1181] [RISC-V] Improve sequences to generate -1, 1 in some cases.

https://gcc.gnu.org/g:1d90f8c7933eb225e26b7598960bc220a582c452 commit r16-1181-g1d90f8c7933eb225e26b7598960bc220a582c452 Author: Jeff Law Date: Thu Jun 5 06:17:25 2025 -0600 [RISC-V] Improve sequences to generate -1, 1 in some cases. This patch has a minor improvement to if-conver

[gcc r16-1105] [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.

https://gcc.gnu.org/g:28106a0c5d18173832d8013dccbb6fcc71646868 commit r16-1105-g28106a0c5d18173832d8013dccbb6fcc71646868 Author: Dongyan Chen Date: Wed Jun 4 08:03:31 2025 -0600 [PATCH] RISC-V: Imply zicsr for svade and svadu extensions. This patch implies zicsr for svade and svad

[gcc r16-1104] [PATCH v2] RISC-V: Add svbare extension.

https://gcc.gnu.org/g:07e3ed74a2b648c0ce8e823bbf5bd8f23383efa1 commit r16-1104-g07e3ed74a2b648c0ce8e823bbf5bd8f23383efa1 Author: Dongyan Chen Date: Wed Jun 4 07:57:01 2025 -0600 [PATCH v2] RISC-V: Add svbare extension. This patch support svbare extension, which is an extension in

[gcc r16-1062] [PATCH] RISC-V: Add smcntrpmf extension.

https://gcc.gnu.org/g:7f1ee85470780ffd0542819c53fb7f7f3d05c9a4 commit r16-1062-g7f1ee85470780ffd0542819c53fb7f7f3d05c9a4 Author: Dongyan Chen Date: Mon Jun 2 13:30:29 2025 -0600 [PATCH] RISC-V: Add smcntrpmf extension. This patch support smcntrpmf extension[1]. To enable GCC t

[gcc r16-1043] [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mode.c

https://gcc.gnu.org/g:d3ddc93a9daa0924cf939508d192999487a9dd4c commit r16-1043-gd3ddc93a9daa0924cf939508d192999487a9dd4c Author: Liao Shihua Date: Sun Jun 1 21:11:25 2025 -0600 [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mode.c This patch fixes the typo in the test ca

[gcc r16-902] [RISC-V] Add andi+bclr synthesis

https://gcc.gnu.org/g:c86125a62d153965a7d7eb17a2bd0d0507326fde commit r16-902-gc86125a62d153965a7d7eb17a2bd0d0507326fde Author: Shreya Munnangi Date: Tue May 27 06:43:29 2025 -0600 [RISC-V] Add andi+bclr synthesis So this patch from Shreya adds the ability to use andi + a series o

[gcc r16-865] [RISC-V] shift+and+shift for logical and synthesis

https://gcc.gnu.org/g:2e2557d160cc0b893a7bcad1bee1683ad948dc60 commit r16-865-g2e2557d160cc0b893a7bcad1bee1683ad948dc60 Author: Shreya Munnangi Date: Sat May 24 13:52:55 2025 -0600 [RISC-V] shift+and+shift for logical and synthesis The next chunk of Shreya's work. For thi

[gcc r16-825] [RISC-V] Clear both upper and lower bits using 3 shifts

https://gcc.gnu.org/g:65f27c18e349e2ccdfac34cef8640d8c6ca1d3c1 commit r16-825-g65f27c18e349e2ccdfac34cef8640d8c6ca1d3c1 Author: Shreya Munnangi Date: Thu May 22 11:51:01 2025 -0600 [RISC-V] Clear both upper and lower bits using 3 shifts So the next step in Shreya's work. In the p

[gcc r16-824] [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

https://gcc.gnu.org/g:c77085970ec98916e12e079a5a9d9530b86aae71 commit r16-824-gc77085970ec98916e12e079a5a9d9530b86aae71 Author: Siarhei Volkau Date: Thu May 22 08:52:17 2025 -0600 [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32 Patch is originally from Siarhei

[gcc r16-814] [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.

https://gcc.gnu.org/g:d8636b05c559e6f060e16652bb10c59d9fb0fb54 commit r16-814-gd8636b05c559e6f060e16652bb10c59d9fb0fb54 Author: Dongyan Chen Date: Wed May 21 21:46:52 2025 -0600 [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level. Failed testcas

[gcc r16-813] [RISC-V] Clear high or low bits using shift pairs

https://gcc.gnu.org/g:b3c778e858497f2b7f37fa8a3101854361c025da commit r16-813-gb3c778e858497f2b7f37fa8a3101854361c025da Author: Shreya Munnangi Date: Wed May 21 18:49:14 2025 -0600 [RISC-V] Clear high or low bits using shift pairs So the first special case of clearing bits from Sh

[gcc r16-810] [PATCH] configure: Always add pre-installed header directories to search path

https://gcc.gnu.org/g:dff727b2c28c52e90e0bd61957d15f907494b245 commit r16-810-gdff727b2c28c52e90e0bd61957d15f907494b245 Author: Stephanos Ioannidis Date: Wed May 21 17:28:36 2025 -0600 [PATCH] configure: Always add pre-installed header directories to search path configure script

[gcc r16-808] [RISC-V] Improve (x << C1) + C2 split code

https://gcc.gnu.org/g:0bed343a2a640c7be4a1970d303098ccf62bd1c6 commit r16-808-g0bed343a2a640c7be4a1970d303098ccf62bd1c6 Author: Jeff Law Date: Wed May 21 16:04:58 2025 -0600 [RISC-V] Improve (x << C1) + C2 split code I wrote this a couple months ago to fix an instruction count reg

[gcc r16-807] [RISC-V][PR target/120368] Fix 32bit shift on rv64

https://gcc.gnu.org/g:8459c546197dc9178d250994db021b36405f1bd6 commit r16-807-g8459c546197dc9178d250994db021b36405f1bd6 Author: Jeff Law Date: Wed May 21 14:15:23 2025 -0600 [RISC-V][PR target/120368] Fix 32bit shift on rv64 So a followup to last week's bugfix. In last week's cha

[gcc r16-768] [RISC-V] Infrastructure of synthesizing logical AND with constant

https://gcc.gnu.org/g:5568277c005f5edda0ce444e11abd1d5845d6ee7 commit r16-768-g5568277c005f5edda0ce444e11abd1d5845d6ee7 Author: Shreya Munnangi Date: Tue May 20 20:15:42 2025 -0600 [RISC-V] Infrastructure of synthesizing logical AND with constant So this is the next step on the pa

[gcc r16-763] [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the sa

https://gcc.gnu.org/g:18f272ec3364bcffac2d798a3a744ff2d4c0f7d5 commit r16-763-g18f272ec3364bcffac2d798a3a744ff2d4c0f7d5 Author: Umesh Kalappa Date: Tue May 20 11:57:00 2025 -0600 [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same.

[gcc r16-762] [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performanc

https://gcc.gnu.org/g:1186a2bd6e187d512030233171293ee87b608189 commit r16-762-g1186a2bd6e187d512030233171293ee87b608189 Author: Umesh Kalappa Date: Tue May 20 11:50:46 2025 -0600 [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix false positive from Wuninitialized

https://gcc.gnu.org/g:7b6a39a58c37fe584659bc74e402aa57e2b1d958 commit 7b6a39a58c37fe584659bc74e402aa57e2b1d958 Author: Jeff Law Date: Mon May 19 12:00:56 2025 -0600 [RISC-V] Fix false positive from Wuninitialized As Mark and I independently tripped, there's a Wuninitialized issue

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid multiple assignments to output object

https://gcc.gnu.org/g:7f8c70a00f2cbf6bd19566e8b0977ec14b51cb3a commit 7f8c70a00f2cbf6bd19566e8b0977ec14b51cb3a Author: Jeff Law Date: Mon May 19 20:31:27 2025 -0600 [RISC-V] Avoid multiple assignments to output object This is the next batch of changes to reduce multiple assignment

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]

https://gcc.gnu.org/g:d64108265568594f7f175f5cef574216e686918e commit d64108265568594f7f175f5cef574216e686918e Author: Pan Li Date: Mon May 19 10:06:35 2025 +0800 RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC] Tweak the asm check with define T uint8_t for addin

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:7d174b97ab2023dac6db77c43d81f3bb3ca9a768 commit 7d174b97ab2023dac6db77c43d81f3bb3ca9a768 Author: Pan Li Date: Sun May 18 19:53:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:4935cb10803cc28b9f3aa07023c60d9a7da7a7b0 commit 4935cb10803cc28b9f3aa07023c60d9a7da7a7b0 Author: Pan Li Date: Sun May 18 20:09:05 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:891d92d8d2bd511b6b40e97a356660aaa7a2aacb commit 891d92d8d2bd511b6b40e97a356660aaa7a2aacb Author: Pan Li Date: Sun May 18 17:07:37 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:31e78aff611135c5e94da67666376305f51e336b commit 31e78aff611135c5e94da67666376305f51e336b Author: Pan Li Date: Sun May 18 20:02:11 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:dc775ce6eb3637befd433b21d85fd433a5ce5eac commit dc775ce6eb3637befd433b21d85fd433a5ce5eac Author: Pan Li Date: Sun May 18 17:17:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for vec_dupli

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:86049f5212dd4189f200a699c9d111c14f66d389 commit 86049f5212dd4189f200a699c9d111c14f66d389 Author: Pan Li Date: Sun May 18 16:49:29 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost

https://gcc.gnu.org/g:2da24518aa7eba93ada0ce353b3e598d7a8cde10 commit 2da24518aa7eba93ada0ce353b3e598d7a8cde10 Author: Pan Li Date: Sun May 18 16:41:01 2025 +0800 RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc r16-753] [RISC-V] Avoid multiple assignments to output object

https://gcc.gnu.org/g:9de7d374323eea212aa1ffb2208a0c7cfcf46f51 commit r16-753-g9de7d374323eea212aa1ffb2208a0c7cfcf46f51 Author: Jeff Law Date: Mon May 19 20:31:27 2025 -0600 [RISC-V] Avoid multiple assignments to output object This is the next batch of changes to reduce multiple a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed][RISC-V][PR target/120333] Remove bogus bext pattern

https://gcc.gnu.org/g:1313b33eae83619e465e9053a1d105e623e78e2b commit 1313b33eae83619e465e9053a1d105e623e78e2b Author: Jeff Law Date: Mon May 19 16:55:15 2025 -0600 [committed][RISC-V][PR target/120333] Remove bogus bext pattern I goof'd when doing analysis of missed bext cases.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix the warning of temporary object dangling references.

https://gcc.gnu.org/g:03e297fb5688ff731b60799258d255db84429abd commit 03e297fb5688ff731b60799258d255db84429abd Author: Dongyan Chen Date: Mon May 19 15:17:12 2025 +0800 RISC-V: Fix the warning of temporary object dangling references. During the GCC compilation, some warnings about

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc

https://gcc.gnu.org/g:ec6b06a19f450fb0c419d0384c8c393bab7c37f5 commit ec6b06a19f450fb0c419d0384c8c393bab7c37f5 Author: zhusonghe Date: Mon May 19 10:43:48 2025 +0800 RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc The variables `major` and `minor` in `gen-riscv-ext-t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

https://gcc.gnu.org/g:fd457d64ad74643e5bab355aefc28ef68a071a58 commit fd457d64ad74643e5bab355aefc28ef68a071a58 Author: Kito Cheng Date: Mon May 12 14:36:07 2025 +0800 RISC-V: Add new operand constraint: cR This commit introduces a new operand constraint `cR` for the RISC-V arc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Zilsd code gen

https://gcc.gnu.org/g:5a6d03fdc642418938b910c8fd7f35c29e7f6ed1 commit 5a6d03fdc642418938b910c8fd7f35c29e7f6ed1 Author: Kito Cheng Date: Mon May 12 02:38:39 2025 -0700 RISC-V: Support Zilsd code gen This commit adds the code gen support for Zilsd, which is a newly added extensi

[gcc r16-740] [committed][RISC-V][PR target/120333] Remove bogus bext pattern

https://gcc.gnu.org/g:38fa6c0455ec14f2f42310a817b90765ad894aa4 commit r16-740-g38fa6c0455ec14f2f42310a817b90765ad894aa4 Author: Jeff Law Date: Mon May 19 16:55:15 2025 -0600 [committed][RISC-V][PR target/120333] Remove bogus bext pattern I goof'd when doing analysis of missed bext

[gcc r16-735] [RISC-V] Fix false positive from Wuninitialized

https://gcc.gnu.org/g:cbc258cd318756db8b5f0e4055dd8f1c1d618d22 commit r16-735-gcbc258cd318756db8b5f0e4055dd8f1c1d618d22 Author: Jeff Law Date: Mon May 19 12:00:56 2025 -0600 [RISC-V] Fix false positive from Wuninitialized As Mark and I independently tripped, there's a Wuninitializ

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Regen riscv-ext.opt.urls

https://gcc.gnu.org/g:a4d3735c33c133d9eb7d029cf2525f575b7e3f85 commit a4d3735c33c133d9eb7d029cf2525f575b7e3f85 Author: Kito Cheng Date: Wed May 14 23:19:17 2025 +0800 RISC-V: Regen riscv-ext.opt.urls gcc/ChangeLog: * config/riscv/riscv-ext.opt.urls: Regenerate.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vector duplicate for expand_const_vector [NFC]

https://gcc.gnu.org/g:11dcc4942eb0edf04ebe897427a938640e56bea2 commit 11dcc4942eb0edf04ebe897427a938640e56bea2 Author: Pan Li Date: Wed Apr 16 15:47:21 2025 +0800 RISC-V: Extract vector duplicate for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about 50

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