https://gcc.gnu.org/g:b3df1cb98ddf0975d10ba741a61a5d8ea97c339b
commit b3df1cb98ddf0975d10ba741a61a5d8ea97c339b
Author: Pan Li <pan2...@intel.com>
Date: Thu Jul 3 17:07:44 2025 +0800
RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vsadd.vv to the
vsadd.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_SAT_S_ADD(T, UT, MIN, MAX) \
T \
test_##T##_sat_add (T x, T y) \
{ \
T sum = (UT)x + (UT)y; \
return (x ^ y) < 0 \
? sum \
: (sum ^ x) >= 0 \
? sum \
: x < 0 ? MIN : MAX; \
}
DEF_SAT_S_ADD(int32_t, uint32_t, INT32_MIN, INT32_MAX)
DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add)
Before this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
14 │ slli a3,a3,32
15 │ srli a3,a3,32
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
18 │ vle32.v v1,0(a1)
19 │ slli a4,a5,2
20 │ sub a3,a3,a5
21 │ add a1,a1,a4
22 │ vsadd.vv v1,v1,v2
23 │ vse32.v v1,0(a0)
24 │ add a0,a0,a4
25 │ bne a3,zero,.L3
After this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ slli a3,a3,32
13 │ srli a3,a3,32
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
16 │ vle32.v v1,0(a1)
17 │ slli a4,a5,2
18 │ sub a3,a3,a5
19 │ add a1,a1,a4
20 │ vsadd.vx v1,v1,a2
21 │ vse32.v v1,0(a0)
22 │ add a0,a0,a4
23 │ bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add
new case SS_PLUS.
(expand_vx_binary_vec_vec_dup): Ditto.
* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
* config/riscv/vector-iterators.md: Add new op ss_plus.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit 0601f461649323c7d6c7bb33c6839f60949116c2)
Diff:
---
gcc/config/riscv/riscv-v.cc | 2 ++
gcc/config/riscv/riscv.cc | 1 +
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index ce1633c72dee..a5ab8dd4e2fe 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5544,6 +5544,7 @@ expand_vx_binary_vec_dup_vec (rtx op_0, rtx op_1, rtx
op_2,
case SMIN:
case UMIN:
case US_PLUS:
+ case SS_PLUS:
icode = code_for_pred_scalar (code, mode);
break;
case MINUS:
@@ -5584,6 +5585,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx
op_2,
case UMIN:
case US_PLUS:
case US_MINUS:
+ case SS_PLUS:
icode = code_for_pred_scalar (code, mode);
break;
default:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 167e78d41ef4..ecdb61e18992 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3997,6 +3997,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
case UMOD:
case US_PLUS:
case US_MINUS:
+ case SS_PLUS:
*total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
break;
default:
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 782544423c41..fd0959c1a4b4 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,11 +4042,11 @@
])
(define_code_iterator any_int_binop_no_shift_v_vdup [
- plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus
us_minus
+ plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus
us_minus ss_plus
])
(define_code_iterator any_int_binop_no_shift_vdup_v [
- plus minus and ior xor mult smax umax smin umin us_plus
+ plus minus and ior xor mult smax umax smin umin us_plus ss_plus
])
(define_code_iterator any_int_unop [neg not])
