https://gcc.gnu.org/g:b2af07bac21862d038bc1583cff97c2f3fb99e74
commit r16-1520-gb2af07bac21862d038bc1583cff97c2f3fb99e74
Author: Jiawei
Date: Mon Jun 16 11:21:29 2025 +0800
RISC-V: Update Profiles string in RV23.
Add b-ext in RVA/B23 as independent extension flags and add supm in
https://gcc.gnu.org/g:14454881497004b365d3b8412b4709109b77857f
commit r16-1519-g14454881497004b365d3b8412b4709109b77857f
Author: Takayuki 'January June' Suwa
Date: Sun Jun 15 18:00:50 2025 +0900
xtensa: Revert "xtensa: Eliminate unwanted reg-reg moves during DFmode
input reloads"
https://gcc.gnu.org/g:f4ebc9b7b1a1f3270eafe649c559dedc94e0553d
commit r16-1518-gf4ebc9b7b1a1f3270eafe649c559dedc94e0553d
Author: Takayuki 'January June' Suwa
Date: Sat Jun 14 20:30:55 2025 +0900
xtensa: Revert "xtensa: Eliminate unnecessary general-purpose reg-reg moves"
Due to im
https://gcc.gnu.org/g:5715865108d7e76bea4cceace38e91b9a28558f8
commit r16-1517-g5715865108d7e76bea4cceace38e91b9a28558f8
Author: Jiawei
Date: Fri Jun 13 18:25:56 2025 +0800
simplify-rtx.cc:Simplify XOR(AND(ROTATE(~1) A) ASHIFT(1 A)) to IOR.
This patch adds a new simplification rul
https://gcc.gnu.org/g:50034d8f109a4d40c5bd63b63d8e8c8d3ea69e56
commit r16-1514-g50034d8f109a4d40c5bd63b63d8e8c8d3ea69e56
Author: Pan Li
Date: Sat Jun 14 22:32:23 2025 +0800
RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR
cost 0, 2 and 15
Add asm dump check
https://gcc.gnu.org/g:afe3401f2e73e21d0e54ea8529642e37ae4a23d5
commit r16-1515-gafe3401f2e73e21d0e54ea8529642e37ae4a23d5
Author: Pan Li
Date: Sat Jun 14 22:34:36 2025 +0800
RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR
cost 0, 1 and 2
Add asm dump check
https://gcc.gnu.org/g:7f153b96aa84773e7b18cf66db73afab55850c2a
commit r16-1513-g7f153b96aa84773e7b18cf66db73afab55850c2a
Author: Pan Li
Date: Sat Jun 14 22:29:40 2025 +0800
RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost
This patch would like to combine the vec_