https://gcc.gnu.org/g:14454881497004b365d3b8412b4709109b77857f
commit r16-1519-g14454881497004b365d3b8412b4709109b77857f
Author: Takayuki 'January June' Suwa <jjsuwa_sys3...@yahoo.co.jp>
Date: Sun Jun 15 18:00:50 2025 +0900
xtensa: Revert "xtensa: Eliminate unwanted reg-reg moves during DFmode
input reloads"
Since there are no unwanted reg-reg moves during DFmode input reloads in
recent GCCs, the previously committed patch
"xtensa: eliminate unwanted reg-reg moves during DFmode input reloads"
(commit cfad4856fa46abc878934a9433d0bfc2482ccf00) is no longer necessary
and is therefore being reverted.
gcc/ChangeLog:
* config/xtensa/predicates.md (reload_operand):
Remove.
* config/xtensa/xtensa.md:
Remove the peephole2 pattern that was previously added.
Diff:
---
gcc/config/xtensa/predicates.md | 13 -------------
gcc/config/xtensa/xtensa.md | 30 ------------------------------
2 files changed, 43 deletions(-)
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index aad4146074af..9aeaba6ad723 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -183,19 +183,6 @@
(and (match_code "const_int")
(match_test "xtensa_mem_offset (INTVAL (op), SFmode)")))
-(define_predicate "reload_operand"
- (match_code "mem")
-{
- const_rtx addr = XEXP (op, 0);
- if (REG_P (addr))
- return REGNO (addr) == A1_REG;
- if (GET_CODE (addr) == PLUS)
- return REG_P (XEXP (addr, 0))
- && REGNO (XEXP (addr, 0)) == A1_REG
- && CONST_INT_P (XEXP (addr, 1));
- return false;
-})
-
(define_predicate "branch_operator"
(match_code "eq,ne,lt,ge"))
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 3064a44f9b55..4c4270ae8bcb 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -3345,36 +3345,6 @@
(const_int 8)
(const_int 9))))])
-(define_peephole2
- [(set (match_operand:SI 0 "register_operand")
- (match_operand:SI 6 "reload_operand"))
- (set (match_operand:SI 1 "register_operand")
- (match_operand:SI 7 "reload_operand"))
- (set (match_operand:SF 2 "register_operand")
- (match_operand:SF 4 "register_operand"))
- (set (match_operand:SF 3 "register_operand")
- (match_operand:SF 5 "register_operand"))]
- "REGNO (operands[0]) == REGNO (operands[4])
- && REGNO (operands[1]) == REGNO (operands[5])
- && peep2_reg_dead_p (4, operands[0])
- && peep2_reg_dead_p (4, operands[1])"
- [(set (match_dup 2)
- (match_dup 6))
- (set (match_dup 3)
- (match_dup 7))]
-{
- HARD_REG_SET regs;
- int i;
- CLEAR_HARD_REG_SET (regs);
- for (i = 0; i <= 3; ++i)
- if (TEST_HARD_REG_BIT (regs, REGNO (operands[i])))
- FAIL;
- else
- SET_HARD_REG_BIT (regs, REGNO (operands[i]));
- operands[6] = gen_rtx_MEM (SFmode, XEXP (operands[6], 0));
- operands[7] = gen_rtx_MEM (SFmode, XEXP (operands[7], 0));
-})
-
(define_split
[(clobber (match_operand 0 "register_operand"))]
"HARD_REGISTER_P (operands[0])
