[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

https://gcc.gnu.org/g:3cbfc97902cc85ef0591c77bbdb3427447db1a59 commit 3cbfc97902cc85ef0591c77bbdb3427447db1a59 Author: Pan Li Date: Tue Jul 23 11:18:48 2024 +0800 RISC-V: Implement the quad and oct .SAT_TRUNC for scalar This patch would like to implement the quad and oct .SAT_TRUN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc

https://gcc.gnu.org/g:540c6b796fe3b6efb51a788cae511ef15b62801c commit 540c6b796fe3b6efb51a788cae511ef15b62801c Author: Jeff Law Date: Sun Aug 18 16:55:52 2024 -0600 [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc This fixes two general ubsan issues in ext-dce, both related

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

https://gcc.gnu.org/g:2c215f2b3022907b79a4a5caa855ee5f88f129e5 commit 2c215f2b3022907b79a4a5caa855ee5f88f129e5 Author: Pan Li Date: Sat Aug 17 19:27:11 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

https://gcc.gnu.org/g:22f0e0f7d321251423a640c5f2b82987917b6d81 commit 22f0e0f7d321251423a640c5f2b82987917b6d81 Author: Pan Li Date: Fri Aug 9 10:26:32 2024 +0800 RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278] For QI/HImode of .SAT_ADD, the operan

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

https://gcc.gnu.org/g:370eaa82697d65d92d5a6270978e18b777bdcfbe commit 370eaa82697d65d92d5a6270978e18b777bdcfbe Author: Pan Li Date: Sat Aug 17 18:04:00 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Avoid right shifting signed value on ext-dce.cc

https://gcc.gnu.org/g:821e603d560221ec4ab517ce1eb1b0152d9c1eac commit 821e603d560221ec4ab517ce1eb1b0152d9c1eac Author: Jeff Law Date: Sat Aug 17 15:10:38 2024 -0600 [committed] Avoid right shifting signed value on ext-dce.cc This is analogous to a prior patch to ext-dce which fixe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

https://gcc.gnu.org/g:c59b5f7b505aae5c1d342a309b6603db2a7c9f19 commit c59b5f7b505aae5c1d342a309b6603db2a7c9f19 Author: Kevin Kirspel Date: Sat Aug 17 14:37:18 2024 -0600 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V The attach patch is specific to the RTEMS RI

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

https://gcc.gnu.org/g:310cb65e2e93e90d5258c60733e1b70f0c8a7e88 commit 310cb65e2e93e90d5258c60733e1b70f0c8a7e88 Author: Jin Ma Date: Sat Aug 17 10:18:03 2024 -0600 RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics When rs1 is the immediate 0, the following ICE

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116282] Stabilize pattern conditions

https://gcc.gnu.org/g:36ad5c69a273cb36accd27e70423c81cbd7fbcf9 commit 36ad5c69a273cb36accd27e70423c81cbd7fbcf9 Author: Jeff Law Date: Sat Aug 17 09:52:55 2024 -0600 [RISC-V][PR target/116282] Stabilize pattern conditions So as expected the core problem with target/116282 is that t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker

https://gcc.gnu.org/g:5b2f688a7fad7b06e4f4fa070373e2781f8b4494 commit 5b2f688a7fad7b06e4f4fa070373e2781f8b4494 Author: Jin Ma Date: Sat Aug 17 09:29:11 2024 -0600 RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker When compiling an interface for rounding of type 'vf

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix incorrect operand for vwsll auto-vect

https://gcc.gnu.org/g:457adc650d8fdaf6bc153930bf60038189d7 commit 457adc650d8fdaf6bc153930bf60038189d7 Author: Pan Li Date: Sat Aug 17 09:25:58 2024 -0600 RISC-V: Bugfix incorrect operand for vwsll auto-vect This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add auto-vect pattern for vector rotate shift

https://gcc.gnu.org/g:ed5cb5a783e2d7aab117bf575e45089a86d4e3c4 commit ed5cb5a783e2d7aab117bf575e45089a86d4e3c4 Author: Feng Wang Date: Sat Aug 17 08:40:42 2024 -0600 RISC-V: Add auto-vect pattern for vector rotate shift This patch add the vector rotate shift pattern for auto-vect.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

https://gcc.gnu.org/g:168bc423824158a6933c06b1ac8a03dbf1736ac6 commit 168bc423824158a6933c06b1ac8a03dbf1736ac6 Author: 曾治金 Date: Wed Aug 14 14:06:23 2024 +0800 RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305] This patch is to fix the bug (BugId:116305) introduced by

[gcc r13-8982] Compare loop bounds in ipa-icf

https://gcc.gnu.org/g:e469654e5e7bdd823c5aa996075e903c6b4d47e2 commit r13-8982-ge469654e5e7bdd823c5aa996075e903c6b4d47e2 Author: Jan Hubicka Date: Mon Aug 19 17:10:25 2024 +0200 Compare loop bounds in ipa-icf Hi, this testcase shows another poblem with missing comparators for

[gcc r15-3028] m68k: Add -mlra

https://gcc.gnu.org/g:c4971bae71cf4d6bb0b458dd9d457ec57d14a4f4 commit r15-3028-gc4971bae71cf4d6bb0b458dd9d457ec57d14a4f4 Author: Andreas Schwab Date: Mon Aug 19 20:59:13 2024 +0200 m68k: Add -mlra PR target/113939 * config/m68k/m68k.opt (mlra): New target optio

[gcc(refs/users/meissner/heads/work176-libs)] Update ChangeLog.*

https://gcc.gnu.org/g:6a2d250899a3691fe55dddf3cf671d49de2d88bd commit 6a2d250899a3691fe55dddf3cf671d49de2d88bd Author: Michael Meissner Date: Mon Aug 19 14:44:50 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.libs | 210 - 1 file

[gcc(refs/users/meissner/heads/work176-libs)] Do not add -mvsx when testing the float128 support.

https://gcc.gnu.org/g:a10b0df9be3c909e5adc0d13fe2f4c89e465a8e6 commit a10b0df9be3c909e5adc0d13fe2f4c89e465a8e6 Author: Michael Meissner Date: Mon Aug 19 14:42:27 2024 -0400 Do not add -mvsx when testing the float128 support. Currently, we add -mvsx when building the float128 suppo

[gcc(refs/users/meissner/heads/work176-libs)] Do not add -mvsx when building libgcc float128 support.

https://gcc.gnu.org/g:18edb686452a6217166adc336a42eec1619e5cf0 commit 18edb686452a6217166adc336a42eec1619e5cf0 Author: Michael Meissner Date: Mon Aug 19 14:38:05 2024 -0400 Do not add -mvsx when building libgcc float128 support. Currently, we add -mvsx when building the float128 s

[gcc(refs/users/meissner/heads/work176-libs)] Do not build IEEE 128-bit libstdc++ support if VSX is not available.

https://gcc.gnu.org/g:c698591d93c802faf42befb1cfdbf7da1e599373 commit c698591d93c802faf42befb1cfdbf7da1e599373 Author: Michael Meissner Date: Mon Aug 19 14:34:16 2024 -0400 Do not build IEEE 128-bit libstdc++ support if VSX is not available. If you build a little endian compiler a

[gcc(refs/users/meissner/heads/work176-libs)] Do not build IEEE 128-bit libgfortran support if VSX is not available.

https://gcc.gnu.org/g:5a17794170f2ae8a3e81f3d4c7e62e5f6abbeeaa commit 5a17794170f2ae8a3e81f3d4c7e62e5f6abbeeaa Author: Michael Meissner Date: Mon Aug 19 14:32:54 2024 -0400 Do not build IEEE 128-bit libgfortran support if VSX is not available. If you build a little endian compiler

[gcc(refs/users/meissner/heads/work176-vpair)] Update ChangeLog.*

https://gcc.gnu.org/g:83e3e4b42b551cbf6e544a2d1fb4bf63f8d95d0c commit 83e3e4b42b551cbf6e544a2d1fb4bf63f8d95d0c Author: Michael Meissner Date: Mon Aug 19 14:27:08 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.vpair | 127 +++- 1 file

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair optimizations.

https://gcc.gnu.org/g:a2ecfd5d0a177a8c3cb187fafdb807e98a4b58a8 commit a2ecfd5d0a177a8c3cb187fafdb807e98a4b58a8 Author: Michael Meissner Date: Mon Aug 19 14:24:38 2024 -0400 Add vector pair optimizations. 2024-08-19 Michael Meissner gcc/ * config/rs6000

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair init and splat.

https://gcc.gnu.org/g:19677035f937f71409fdf6cc52999ab1e7e0c25f commit 19677035f937f71409fdf6cc52999ab1e7e0c25f Author: Michael Meissner Date: Mon Aug 19 14:23:29 2024 -0400 Add vector pair init and splat. 2024-08-19 Michael Meissner gcc/ * config/rs600

[gcc(refs/users/meissner/heads/work176-vpair)] Add support for vector pair fma operations.

https://gcc.gnu.org/g:64af04ceb49a577e8c263db5e1ac31fb0b8c18b7 commit 64af04ceb49a577e8c263db5e1ac31fb0b8c18b7 Author: Michael Meissner Date: Mon Aug 19 14:22:38 2024 -0400 Add support for vector pair fma operations. 2024-08-19 Michael Meissner gcc/ *

[gcc(refs/users/meissner/heads/work176-vpair)] Add support for vector pair unary and binary operations.

https://gcc.gnu.org/g:843b0025117e9a3c3a3bb57b5dc05c149b94575e commit 843b0025117e9a3c3a3bb57b5dc05c149b94575e Author: Michael Meissner Date: Mon Aug 19 14:21:35 2024 -0400 Add support for vector pair unary and binary operations. 2024-08-19 Michael Meissner gcc/

[gcc(refs/users/meissner/heads/work176-tar)] Update ChangeLog.*

https://gcc.gnu.org/g:15ff7216870b8c3689c848ab8d42d67598c6337d commit 15ff7216870b8c3689c848ab8d42d67598c6337d Author: Michael Meissner Date: Mon Aug 19 14:19:19 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 83 ++- 1 file

[gcc(refs/users/meissner/heads/work176-tar)] Add support for the TAR register.

https://gcc.gnu.org/g:987957c82206af4bf69175c7438fe9d3de5a3cc0 commit 987957c82206af4bf69175c7438fe9d3de5a3cc0 Author: Michael Meissner Date: Mon Aug 19 14:16:09 2024 -0400 Add support for the TAR register. 2024-08-19 Michael Meissner gcc/ * config/rs6

[gcc(refs/users/meissner/heads/work176-tar)] Remove SPR alternatives for move insns.

https://gcc.gnu.org/g:1eaca9796aaad6e085323f03fd523d087ee659db commit 1eaca9796aaad6e085323f03fd523d087ee659db Author: Michael Meissner Date: Mon Aug 19 14:17:13 2024 -0400 Remove SPR alternatives for move insns. 2024-08-19 Michael Meissner * config/rs6000/rs60

[gcc(refs/users/meissner/heads/work176-bugs)] Update ChagneLog.bugs

https://gcc.gnu.org/g:74a68d9476981f47d53073131b05cfdd28c28a64 commit 74a68d9476981f47d53073131b05cfdd28c28a64 Author: Michael Meissner Date: Mon Aug 19 14:12:25 2024 -0400 Update ChagneLog.bugs Diff: --- gcc/ChangeLog.bugs | 94 +- 1 f

[gcc(refs/users/meissner/heads/work176-bugs)] Optimize splat of a V2DF/V2DI extract with constant element

https://gcc.gnu.org/g:d4e863527f6453d567400381cb3df53fa3c03f22 commit d4e863527f6453d567400381cb3df53fa3c03f22 Author: Michael Meissner Date: Mon Aug 19 14:10:44 2024 -0400 Optimize splat of a V2DF/V2DI extract with constant element We had optimizations for splat of a vector extra

[gcc(refs/users/meissner/heads/work176-bugs)] Add better support for shifting vectors with 64-bit elements

https://gcc.gnu.org/g:b79d939912a9826b29603037848503ca56ed2ea8 commit b79d939912a9826b29603037848503ca56ed2ea8 Author: Michael Meissner Date: Mon Aug 19 14:09:32 2024 -0400 Add better support for shifting vectors with 64-bit elements This patch fixes PR target/89213 to allow bette

[gcc/meissner/heads/work176] Merge commit 'refs/users/meissner/heads/work176' of git+ssh

The branch 'meissner/heads/work176' was updated to point to: 248fc70e14e... Merge commit 'refs/users/meissner/heads/work176' of git+ssh It previously pointed to: 5f249111a45... Revert changes Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2677-Add xvrlw support

https://gcc.gnu.org/g:bb360cc7fdb5b20190372b0628b03e25390c0f96 commit bb360cc7fdb5b20190372b0628b03e25390c0f96 Author: Michael Meissner Date: Mon Aug 19 14:00:19 2024 -0400 RFC2677-Add xvrlw support 2024-08-19 Michael Meissner gcc/ * config/rs6000/alti

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2686-Add paddis support

https://gcc.gnu.org/g:c827e64576d202661c6224ff540659ced605297e commit c827e64576d202661c6224ff540659ced605297e Author: Michael Meissner Date: Mon Aug 19 13:59:50 2024 -0400 RFC2686-Add paddis support 2024-08-19 Michael Meissner gcc/ * config/rs6000/con

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2655-Add saturating subtract built-ins

https://gcc.gnu.org/g:5777392dbf05d4fe6ad82405b4cf81055b8bc12f commit 5777392dbf05d4fe6ad82405b4cf81055b8bc12f Author: Michael Meissner Date: Mon Aug 19 13:59:27 2024 -0400 RFC2655-Add saturating subtract built-ins This patch adds support for a saturating subtract built-in functio

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers

https://gcc.gnu.org/g:b9841440d225bf35f9903212cef11b6679c963cc commit b9841440d225bf35f9903212cef11b6679c963cc Author: Michael Meissner Date: Mon Aug 19 13:57:32 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers This patch is a prelimianry patch to add the full 1

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2656-Support load/store vector with right length

https://gcc.gnu.org/g:5a59d920eb3dbcad808d1ed496cb279de9adfa2f commit 5a59d920eb3dbcad808d1ed496cb279de9adfa2f Author: Michael Meissner Date: Mon Aug 19 13:59:03 2024 -0400 RFC2656-Support load/store vector with right length This patch adds support for new instructions that may be

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

https://gcc.gnu.org/g:d5e1fc8ad02bfd5b133b328cbb8d8e51bd247f6b commit d5e1fc8ad02bfd5b133b328cbb8d8e51bd247f6b Author: Michael Meissner Date: Mon Aug 19 13:54:13 2024 -0400 RFC2653-PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruc

[gcc(refs/users/meissner/heads/work176-dmf)] xRFC2653-Add dense math test for new instruction names.

https://gcc.gnu.org/g:ce4973acae8715305b2e8e6bec1bd73eccd1a971 commit ce4973acae8715305b2e8e6bec1bd73eccd1a971 Author: Michael Meissner Date: Mon Aug 19 13:54:59 2024 -0400 xRFC2653-Add dense math test for new instruction names. 2024-08-19 Michael Meissner gcc/testsui

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:621467db4c48a51fa4b26b560f31e32cb5882525 commit 621467db4c48a51fa4b26b560f31e32cb5882525 Author: Michael Meissner Date: Mon Aug 19 13:53:00 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-Add wD constraint.

https://gcc.gnu.org/g:631c2bebb7aad48deba16a5e0d4f02c08f8e56bc commit 631c2bebb7aad48deba16a5e0d4f02c08f8e56bc Author: Michael Meissner Date: Mon Aug 19 13:52:23 2024 -0400 RFC2653-Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers

[gcc(refs/users/meissner/heads/work176-dmf)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:aa3552fcdfe7f9c6103229a5c1a194d4ed625474 commit aa3552fcdfe7f9c6103229a5c1a194d4ed625474 Author: Michael Meissner Date: Mon Aug 19 13:51:56 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC di

[gcc(refs/users/meissner/heads/work176)] Revert changes

https://gcc.gnu.org/g:5f249111a45818b00063a4674c46041805269bf5 commit 5f249111a45818b00063a4674c46041805269bf5 Author: Michael Meissner Date: Mon Aug 19 13:51:17 2024 -0400 Revert changes Diff: --- gcc/config/rs6000/altivec.md | 14 - gcc/config/rs6000/constraints.

[gcc(refs/users/meissner/heads/work176)] RFC2677-Add xvrlw support.

https://gcc.gnu.org/g:11f9bbc963f9096f58f1e57fd3a61476333df2c3 commit 11f9bbc963f9096f58f1e57fd3a61476333df2c3 Author: Michael Meissner Date: Mon Aug 19 13:45:28 2024 -0400 RFC2677-Add xvrlw support. 2024-08-19 Michael Meissner gcc/ * config/rs6000/alt

[gcc(refs/users/meissner/heads/work176)] RFC2655-Add saturating subtract built-ins.

https://gcc.gnu.org/g:251349263ff84a4c5c5b6a712e8c106402405101 commit 251349263ff84a4c5c5b6a712e8c106402405101 Author: Michael Meissner Date: Mon Aug 19 13:43:33 2024 -0400 RFC2655-Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in functi

[gcc(refs/users/meissner/heads/work176)] RFC2686-Add paddis support.

https://gcc.gnu.org/g:0db29e6841be33457118d7888dde0f258c5c360b commit 0db29e6841be33457118d7888dde0f258c5c360b Author: Michael Meissner Date: Mon Aug 19 13:44:27 2024 -0400 RFC2686-Add paddis support. 2024-08-19 Michael Meissner gcc/ * config/rs6000/co

[gcc(refs/users/meissner/heads/work176)] RFC2656-Support load/store vector with right length.

https://gcc.gnu.org/g:56a9db5160a34db170f68370c1f0848f2969742f commit 56a9db5160a34db170f68370c1f0848f2969742f Author: Michael Meissner Date: Mon Aug 19 13:42:46 2024 -0400 RFC2656-Support load/store vector with right length. This patch adds support for new instructions that may b

[gcc(refs/users/meissner/heads/work176)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

https://gcc.gnu.org/g:9bb7924857212ebaed7d46832d148c50461412e6 commit 9bb7924857212ebaed7d46832d148c50461412e6 Author: Michael Meissner Date: Mon Aug 19 13:41:01 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full

[gcc(refs/users/meissner/heads/work176)] RFC2653-Add dense math test for new instruction names.

https://gcc.gnu.org/g:42a51bfe1a5e19fb3905bead97b777c68674e9c5 commit 42a51bfe1a5e19fb3905bead97b777c68674e9c5 Author: Michael Meissner Date: Mon Aug 19 13:40:32 2024 -0400 RFC2653-Add dense math test for new instruction names. 2024-08-19 Michael Meissner gcc/testsuit

[gcc(refs/users/meissner/heads/work176)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:6a73439005e310de104d07d715b0cd36daa2d681 commit 6a73439005e310de104d07d715b0cd36daa2d681 Author: Michael Meissner Date: Mon Aug 19 13:39:53 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work176)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:2f6844a7aa601f68f9450134f46cb8fda5715b57 commit 2f6844a7aa601f68f9450134f46cb8fda5715b57 Author: Michael Meissner Date: Mon Aug 19 13:39:13 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work176)] RFC2653-Add wD constraint.

https://gcc.gnu.org/g:5b68a1cf7d131e20e82dd1fc33163830e5661062 commit 5b68a1cf7d131e20e82dd1fc33163830e5661062 Author: Michael Meissner Date: Mon Aug 19 13:38:39 2024 -0400 RFC2653-Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers

[gcc(refs/users/meissner/heads/work176)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:3548ae9e3ef2e61267350c7f81b567fc05693297 commit 3548ae9e3ef2e61267350c7f81b567fc05693297 Author: Michael Meissner Date: Mon Aug 19 13:36:44 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC di

[gcc r14-10603] c++: fix ICE in convert_nontype_argument [PR116384]

https://gcc.gnu.org/g:52da8588fd06198edcda81d7acf83ec92ccb63ef commit r14-10603-g52da8588fd06198edcda81d7acf83ec92ccb63ef Author: Marek Polacek Date: Thu Aug 15 11:53:10 2024 -0400 c++: fix ICE in convert_nontype_argument [PR116384] Here we ICE since r14-8291 in C++11/C++14 modes.

[gcc(refs/users/meissner/heads/work176)] Revert changes

https://gcc.gnu.org/g:fa18267733f303996608ccc9940d21663a929d2d commit fa18267733f303996608ccc9940d21663a929d2d Author: Michael Meissner Date: Mon Aug 19 13:34:29 2024 -0400 Revert changes Diff: --- gcc/config/rs6000/constraints.md | 3 - gcc/config/rs6000/mma.md

[gcc(refs/users/meissner/heads/work176)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

https://gcc.gnu.org/g:6cc817c10c29be4958d76da3eda063f7757c71cc commit 6cc817c10c29be4958d76da3eda063f7757c71cc Author: Michael Meissner Date: Mon Aug 19 13:30:17 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full

[gcc(refs/users/meissner/heads/work176)] RFC2653-Add dense math test for new instruction names.

https://gcc.gnu.org/g:5337baaab6eac19696df611a23611d07ca705fd8 commit 5337baaab6eac19696df611a23611d07ca705fd8 Author: Michael Meissner Date: Mon Aug 19 13:27:50 2024 -0400 RFC2653-Add dense math test for new instruction names. 2024-08-19 Michael Meissner gcc/testsuit

[gcc(refs/users/meissner/heads/work176)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

https://gcc.gnu.org/g:b994c1d199b858a92d56739893898f3dd2b6736c commit b994c1d199b858a92d56739893898f3dd2b6736c Author: Michael Meissner Date: Mon Aug 19 13:26:15 2024 -0400 RFC2653-PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruc

[gcc(refs/users/meissner/heads/work176)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:8e9996449f3217a6255968bfae32cced7feaba44 commit 8e9996449f3217a6255968bfae32cced7feaba44 Author: Michael Meissner Date: Mon Aug 19 13:25:14 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work176)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:0d4fd03f8cbe6eb44f17361cd4d1b8f889a89393 commit 0d4fd03f8cbe6eb44f17361cd4d1b8f889a89393 Author: Michael Meissner Date: Mon Aug 19 13:22:38 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC di

[gcc r15-3027] c++: ICE with enum and conversion fn in template [PR115657]

https://gcc.gnu.org/g:53283c3231a7b94e728619cccbf21170fb36b2a8 commit r15-3027-g53283c3231a7b94e728619cccbf21170fb36b2a8 Author: Marek Polacek Date: Thu Aug 15 18:47:29 2024 -0400 c++: ICE with enum and conversion fn in template [PR115657] Here we initialize an enumerator with a c

[gcc r15-3026] c++: fix ICE in convert_nontype_argument [PR116384]

https://gcc.gnu.org/g:8191f15022b0ea44fcb549449b0458d07ae02e0a commit r15-3026-g8191f15022b0ea44fcb549449b0458d07ae02e0a Author: Marek Polacek Date: Thu Aug 15 11:53:10 2024 -0400 c++: fix ICE in convert_nontype_argument [PR116384] Here we ICE since r14-8291 in C++11/C++14 modes.

[gcc(refs/users/meissner/heads/work176-vpair)] Merge commit 'refs/users/meissner/heads/work176-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

https://gcc.gnu.org/g:b9f77deab8b4da60cf36312105b3edb066c5a93c commit b9f77deab8b4da60cf36312105b3edb066c5a93c Merge: 9adc2e6b281 217eac978ad Author: Michael Meissner Date: Mon Aug 19 13:19:53 2024 -0400 Merge commit 'refs/users/meissner/heads/work176-vpair' of git+ssh://gcc.gnu.org/git/g

[gcc(refs/users/meissner/heads/work176-vpair)] Add ChangeLog.vpair and update REVISION.

https://gcc.gnu.org/g:9adc2e6b2815cefe418d4b0af4657795ddfe4df0 commit 9adc2e6b2815cefe418d4b0af4657795ddfe4df0 Author: Michael Meissner Date: Fri Aug 16 20:02:38 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-08-16 Michael Meissner gcc/ * Cha

[gcc/meissner/heads/work176-vpair] (95 commits) Merge commit 'refs/users/meissner/heads/work176-vpair' of g

The branch 'meissner/heads/work176-vpair' was updated to point to: b9f77deab8b... Merge commit 'refs/users/meissner/heads/work176-vpair' of g It previously pointed to: 217eac978ad... Add ChangeLog.vpair and update REVISION. Diff: Summary of changes (added commits): --

[gcc(refs/users/meissner/heads/work176-test)] Merge commit 'refs/users/meissner/heads/work176-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

https://gcc.gnu.org/g:0a2935428aa3e6a7d986e2b07a0b895aba1b0059 commit 0a2935428aa3e6a7d986e2b07a0b895aba1b0059 Merge: 19c0b322453 05975e9bc07 Author: Michael Meissner Date: Mon Aug 19 13:18:15 2024 -0400 Merge commit 'refs/users/meissner/heads/work176-test' of git+ssh://gcc.gnu.org/git/gc

[gcc(refs/users/meissner/heads/work176-test)] Add ChangeLog.test and update REVISION.

https://gcc.gnu.org/g:19c0b322453aacf4a53fe67ff8811a0a2684798e commit 19c0b322453aacf4a53fe67ff8811a0a2684798e Author: Michael Meissner Date: Fri Aug 16 20:06:31 2024 -0400 Add ChangeLog.test and update REVISION. 2024-08-16 Michael Meissner gcc/ * Chan

[gcc/meissner/heads/work176-test] (95 commits) Merge commit 'refs/users/meissner/heads/work176-test' of gi

The branch 'meissner/heads/work176-test' was updated to point to: 0a2935428aa... Merge commit 'refs/users/meissner/heads/work176-test' of gi It previously pointed to: 05975e9bc07... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits):

[gcc(refs/users/meissner/heads/work176-tar)] Merge commit 'refs/users/meissner/heads/work176-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17

https://gcc.gnu.org/g:42ecdd64c126b7afedba43107c30fc4a2b635c8a commit 42ecdd64c126b7afedba43107c30fc4a2b635c8a Merge: 6c8633d3836 f10dbe3d9d2 Author: Michael Meissner Date: Mon Aug 19 13:15:17 2024 -0400 Merge commit 'refs/users/meissner/heads/work176-tar' of git+ssh://gcc.gnu.org/git/gcc

[gcc(refs/users/meissner/heads/work176-tar)] Add ChangeLog.tar and update REVISION.

https://gcc.gnu.org/g:6c8633d383609c501bd96e38fcc9f8b297de179e commit 6c8633d383609c501bd96e38fcc9f8b297de179e Author: Michael Meissner Date: Fri Aug 16 20:03:42 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-08-16 Michael Meissner gcc/ * Chang

[gcc/meissner/heads/work176-tar] (95 commits) Merge commit 'refs/users/meissner/heads/work176-tar' of git

The branch 'meissner/heads/work176-tar' was updated to point to: 42ecdd64c12... Merge commit 'refs/users/meissner/heads/work176-tar' of git It previously pointed to: f10dbe3d9d2... Add ChangeLog.tar and update REVISION. Diff: Summary of changes (added commits): --

[gcc(refs/users/meissner/heads/work176-libs)] Merge commit 'refs/users/meissner/heads/work176-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

https://gcc.gnu.org/g:f4ab5ad347d3547ef20abf22f2d7a53c63a9c663 commit f4ab5ad347d3547ef20abf22f2d7a53c63a9c663 Merge: 3b92cb41e27 f7c2e5662a4 Author: Michael Meissner Date: Mon Aug 19 13:12:37 2024 -0400 Merge commit 'refs/users/meissner/heads/work176-libs' of git+ssh://gcc.gnu.org/git/gc

[gcc(refs/users/meissner/heads/work176-libs)] Add ChangeLog.libs and update REVISION.

https://gcc.gnu.org/g:3b92cb41e27b73f453bc3b851fa3881ff8e69f15 commit 3b92cb41e27b73f453bc3b851fa3881ff8e69f15 Author: Michael Meissner Date: Fri Aug 16 20:05:31 2024 -0400 Add ChangeLog.libs and update REVISION. 2024-08-16 Michael Meissner gcc/ * Chan

[gcc/meissner/heads/work176-libs] (95 commits) Merge commit 'refs/users/meissner/heads/work176-libs' of gi

The branch 'meissner/heads/work176-libs' was updated to point to: f4ab5ad347d... Merge commit 'refs/users/meissner/heads/work176-libs' of gi It previously pointed to: f7c2e5662a4... Add ChangeLog.libs and update REVISION. Diff: Summary of changes (added commits):

[gcc(refs/users/meissner/heads/work176-dmf)] Merge commit 'refs/users/meissner/heads/work176-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17

https://gcc.gnu.org/g:0d03a3fd23b2fe6c2459bc1fee6f164cf758419c commit 0d03a3fd23b2fe6c2459bc1fee6f164cf758419c Merge: 9d15a613c0a 2f5f585dae7 Author: Michael Meissner Date: Mon Aug 19 13:10:13 2024 -0400 Merge commit 'refs/users/meissner/heads/work176-dmf' of git+ssh://gcc.gnu.org/git/gcc

[gcc(refs/users/meissner/heads/work176-dmf)] Add ChangeLog.dmf and update REVISION.

https://gcc.gnu.org/g:9d15a613c0ae6e75837955001ff97c8a665e72db commit 9d15a613c0ae6e75837955001ff97c8a665e72db Author: Michael Meissner Date: Fri Aug 16 20:01:40 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-08-16 Michael Meissner gcc/ * Chang

[gcc/meissner/heads/work176-dmf] (95 commits) Merge commit 'refs/users/meissner/heads/work176-dmf' of git

The branch 'meissner/heads/work176-dmf' was updated to point to: 0d03a3fd23b... Merge commit 'refs/users/meissner/heads/work176-dmf' of git It previously pointed to: 2f5f585dae7... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits): --

[gcc/meissner/heads/work176-bugs] (95 commits) Merge commit 'refs/users/meissner/heads/work176-bugs' of gi

The branch 'meissner/heads/work176-bugs' was updated to point to: bb95d1744c6... Merge commit 'refs/users/meissner/heads/work176-bugs' of gi It previously pointed to: 0ec692e56ea... Add ChangeLog.bugs and update REVISION. Diff: Summary of changes (added commits):

[gcc(refs/users/meissner/heads/work176-bugs)] Add ChangeLog.bugs and update REVISION.

https://gcc.gnu.org/g:1833352955bb5ce263780493e895c6edd23cfd01 commit 1833352955bb5ce263780493e895c6edd23cfd01 Author: Michael Meissner Date: Fri Aug 16 20:04:36 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-08-16 Michael Meissner gcc/ * Chan

[gcc(refs/users/meissner/heads/work176-bugs)] Merge commit 'refs/users/meissner/heads/work176-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

https://gcc.gnu.org/g:bb95d1744c6896582aa054923434e8dccd6f2a1c commit bb95d1744c6896582aa054923434e8dccd6f2a1c Merge: 1833352955b 0ec692e56ea Author: Michael Meissner Date: Mon Aug 19 13:08:44 2024 -0400 Merge commit 'refs/users/meissner/heads/work176-bugs' of git+ssh://gcc.gnu.org/git/gc

[gcc(refs/users/meissner/heads/work176)] Merge commit 'refs/users/meissner/heads/work176' of git+ssh://gcc.gnu.org/git/gcc into me/work176

https://gcc.gnu.org/g:248fc70e14ee9c6a974a44bc0bbbd82d3bb3b8dc commit 248fc70e14ee9c6a974a44bc0bbbd82d3bb3b8dc Merge: 03ac745bc43 04913bc20cb Author: Michael Meissner Date: Mon Aug 19 13:04:41 2024 -0400 Merge commit 'refs/users/meissner/heads/work176' of git+ssh://gcc.gnu.org/git/gcc int

[gcc(refs/users/meissner/heads/work176)] Update ChangeLog.*

https://gcc.gnu.org/g:03ac745bc431b766a951e55d2911ef1f571ccb6b commit 03ac745bc431b766a951e55d2911ef1f571ccb6b Author: Michael Meissner Date: Sat Aug 17 05:40:54 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 49 + 1 file

[gcc(refs/users/meissner/heads/work176)] Add -mcpu=future tuning support.

https://gcc.gnu.org/g:aa65901ff72a56dda008d78e421ff832595306d2 commit aa65901ff72a56dda008d78e421ff832595306d2 Author: Michael Meissner Date: Sat Aug 17 03:24:57 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=powe

[gcc(refs/users/meissner/heads/work176)] Add support for -mcpu=future

https://gcc.gnu.org/g:3031a7ca9367f11554c16c035a8642435a1c147e commit 3031a7ca9367f11554c16c035a8642435a1c147e Author: Michael Meissner Date: Sat Aug 17 03:24:08 2024 -0400 Add support for -mcpu=future This patch adds the support that can be used in developing GCC support for

[gcc(refs/users/meissner/heads/work176)] Update ChangeLog.*

https://gcc.gnu.org/g:df189b69e46ecf12ff284d388fb279d300b78676 commit df189b69e46ecf12ff284d388fb279d300b78676 Author: Michael Meissner Date: Sat Aug 17 01:34:04 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 400 - 1 file

[gcc(refs/users/meissner/heads/work176)] Change TARGET_MODULO to TARGET_POWER9

https://gcc.gnu.org/g:255d09dcd5282a6e931be6fa4d245689e78811cb commit 255d09dcd5282a6e931be6fa4d245689e78811cb Author: Michael Meissner Date: Fri Aug 16 22:41:01 2024 -0400 Change TARGET_MODULO to TARGET_POWER9 As part of the architecture flags patches, this patch changes the use

[gcc(refs/users/meissner/heads/work176)] Update tests to work with architecture flags changes.

https://gcc.gnu.org/g:9e3ab515a72678f56a9b34aa80ce413a99c7bb84 commit 9e3ab515a72678f56a9b34aa80ce413a99c7bb84 Author: Michael Meissner Date: Sat Aug 17 01:27:41 2024 -0400 Update tests to work with architecture flags changes. Two tests used -mvsx to raise the processor level to a

[gcc(refs/users/meissner/heads/work176)] Change TARGET_POPCNTD to TARGET_POWER7

https://gcc.gnu.org/g:2f2353e1a515954f9fe2e0e1e6afd825239f6be7 commit 2f2353e1a515954f9fe2e0e1e6afd825239f6be7 Author: Michael Meissner Date: Fri Aug 16 22:40:12 2024 -0400 Change TARGET_POPCNTD to TARGET_POWER7 As part of the architecture flags patches, this patch changes the use

[gcc(refs/users/meissner/heads/work176)] Change TARGET_CMPB to TARGET_POWER6

https://gcc.gnu.org/g:daa12c0fb7a81a446d45b3e25173fe62cce96c5a commit daa12c0fb7a81a446d45b3e25173fe62cce96c5a Author: Michael Meissner Date: Fri Aug 16 22:39:19 2024 -0400 Change TARGET_CMPB to TARGET_POWER6 As part of the architecture flags patches, this patch changes the use of

[gcc(refs/users/meissner/heads/work176)] Change TARGET_FPRND to TARGET_POWER5X

https://gcc.gnu.org/g:9b740bf277b8db7b96f06d1ccf28d3ef2660c79f commit 9b740bf277b8db7b96f06d1ccf28d3ef2660c79f Author: Michael Meissner Date: Fri Aug 16 22:38:21 2024 -0400 Change TARGET_FPRND to TARGET_POWER5X As part of the architecture flags patches, this patch changes the use

[gcc(refs/users/meissner/heads/work176)] Change TARGET_POPCNTB to TARGET_POWER5

https://gcc.gnu.org/g:d83a1cd5ecc371c87813a2f8a1616d1fca72283d commit d83a1cd5ecc371c87813a2f8a1616d1fca72283d Author: Michael Meissner Date: Fri Aug 16 22:37:10 2024 -0400 Change TARGET_POPCNTB to TARGET_POWER5 As part of the architecture flags patches, this patch changes the use

[gcc(refs/users/meissner/heads/work176)] Do not allow -mvsx to boost processor to power7.

https://gcc.gnu.org/g:eeab60022333b52fefc8b17c56198d934170a8c5 commit eeab60022333b52fefc8b17c56198d934170a8c5 Author: Michael Meissner Date: Fri Aug 16 22:36:24 2024 -0400 Do not allow -mvsx to boost processor to power7. This patch restructures the code so that -mvsx for example

[gcc(refs/users/meissner/heads/work176)] Use architecture flags for defining _ARCH_PWR macros.

https://gcc.gnu.org/g:582584801c3823d194edcece5048b9d4e0cbccf5 commit 582584801c3823d194edcece5048b9d4e0cbccf5 Author: Michael Meissner Date: Fri Aug 16 22:35:24 2024 -0400 Use architecture flags for defining _ARCH_PWR macros. For the newer architectures, this patch changes GCC to

[gcc(refs/users/meissner/heads/work176)] Add rs6000 architecture masks.

https://gcc.gnu.org/g:7a80d6af56554fe3388d59f71341a6c96b5d5d01 commit 7a80d6af56554fe3388d59f71341a6c96b5d5d01 Author: Michael Meissner Date: Fri Aug 16 22:34:18 2024 -0400 Add rs6000 architecture masks. This patch begins the journey to move architecture bits that are not user IS

[gcc(refs/users/meissner/heads/work176)] Add ChangeLog.meissner and REVISION.

https://gcc.gnu.org/g:b04aa92b92c588802feb39d2b0fe8efecb47ded6 commit b04aa92b92c588802feb39d2b0fe8efecb47ded6 Author: Michael Meissner Date: Fri Aug 16 20:00:35 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-08-16 Michael Meissner gcc/ * REVISIO

[gcc/meissner/heads/work176] (80 commits) Merge commit 'refs/users/meissner/heads/work176' of git+ssh

The branch 'meissner/heads/work176' was updated to point to: 248fc70e14e... Merge commit 'refs/users/meissner/heads/work176' of git+ssh It previously pointed to: 04913bc20cb... Update ChangeLog.* Diff: Summary of changes (added commits): --- 248fc70... Merg

[gcc r15-3025] aarch64: Fix ls64 intrinsic availability

https://gcc.gnu.org/g:fceecc511d4918e2b27a0609f8885ec8aba8723d commit r15-3025-gfceecc511d4918e2b27a0609f8885ec8aba8723d Author: Andrew Carlotti Date: Thu Oct 26 15:45:15 2023 +0100 aarch64: Fix ls64 intrinsic availability The availability of ls64 intrinsics and data types were de

[gcc r15-3022] aarch64: Move check_required_extensions

https://gcc.gnu.org/g:baf71ec56b40858c5b2a4cc8481403685d753477 commit r15-3022-gbaf71ec56b40858c5b2a4cc8481403685d753477 Author: Andrew Carlotti Date: Tue Jul 18 16:40:58 2023 +0100 aarch64: Move check_required_extensions Move SVE extension checking functionality to aarch64-builti

[gcc r15-3021] aarch64: Refactor check_required_extensions

https://gcc.gnu.org/g:a4b39dc4bfad2b224cd2041568d469b5724f8f88 commit r15-3021-ga4b39dc4bfad2b224cd2041568d469b5724f8f88 Author: Andrew Carlotti Date: Tue Aug 13 16:15:11 2024 +0100 aarch64: Refactor check_required_extensions Replace TARGET_GENERAL_REGS_ONLY check with an explicit

[gcc r15-3024] aarch64: Fix memtag intrinsic availability

https://gcc.gnu.org/g:4e1b617b35631df4dd6089d4044aa19d0c1adea7 commit r15-3024-g4e1b617b35631df4dd6089d4044aa19d0c1adea7 Author: Andrew Carlotti Date: Tue Jul 18 20:09:38 2023 +0100 aarch64: Fix memtag intrinsic availability The availability of memtag intrinsics and data types wer

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