https://gcc.gnu.org/g:5b2f688a7fad7b06e4f4fa070373e2781f8b4494
commit 5b2f688a7fad7b06e4f4fa070373e2781f8b4494
Author: Jin Ma <ji...@linux.alibaba.com>
Date: Sat Aug 17 09:29:11 2024 -0600
RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker
When compiling an interface for rounding of type 'vfloat16*' without using
zvfh
or zvfhmin, it is not enough to use FLOAT_MODE_P because the type does not
support it. Although the subsequent riscv_validate_vector_type checks will
still fail and throw exceptions, I don't think we should have ICE here.
internal compiler error: in check, at
config/riscv/riscv-vector-builtins-shapes.cc:444
10 | return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl);
| ^~~~~~
0x4191794 internal_error(char const*, ...)
/iothome/jin.ma/code/master/gcc/gcc/diagnostic-global-context.cc:491
0x416ebf5 fancy_abort(char const*, int, char const*)
/iothome/jin.ma/code/master/gcc/gcc/diagnostic.cc:1772
0x220aae6
riscv_vector::build_frm_base::check(riscv_vector::function_checker&) const
/iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins-shapes.cc:444
0x2205323 riscv_vector::function_checker::check()
/iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins.cc:4414
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_vector_float_type_p): New.
* config/riscv/riscv-vector-builtins.cc
(function_instance::any_type_float_p):
Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment.
* config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to
extern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-9.c: New test.
(cherry picked from commit 3f51684ac05f065a87c53d9506400cbe97af6b79)
Diff:
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv.cc | 5 ++++-
gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c | 13 +++++++++++++
4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 124ae2c073a..f8fc2874cbb 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -171,6 +171,7 @@ extern enum memmodel riscv_union_memmodels (enum memmodel,
enum memmodel);
extern bool riscv_reg_frame_related (rtx);
extern void riscv_split_sum_of_two_s12 (HOST_WIDE_INT, HOST_WIDE_INT *,
HOST_WIDE_INT *);
+extern bool riscv_vector_float_type_p (const_tree type);
/* Routines implemented in riscv-c.cc. */
void riscv_cpu_cpp_builtins (cpp_reader *);
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 9f707efa533..41730c483ee 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3497,11 +3497,11 @@ function_instance::operator== (const function_instance
&other) const
bool
function_instance::any_type_float_p () const
{
- if (FLOAT_MODE_P (TYPE_MODE (get_return_type ())))
+ if (riscv_vector_float_type_p (get_return_type ()))
return true;
for (int i = 0; op_info->args[i].base_type != NUM_BASE_TYPES; ++i)
- if (FLOAT_MODE_P (TYPE_MODE (get_arg_type (i))))
+ if (riscv_vector_float_type_p (get_arg_type (i)))
return true;
return false;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 938ec02b750..420037885be 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5898,9 +5898,12 @@ riscv_vector_int_type_p (const_tree type)
return strstr (name, "int") != NULL || strstr (name, "uint") != NULL;
}
-static bool
+bool
riscv_vector_float_type_p (const_tree type)
{
+ if (!riscv_vector_type_p (type))
+ return false;
+
machine_mode mode = TYPE_MODE (type);
if (VECTOR_MODE_P (mode))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
new file mode 100644
index 00000000000..20ae9ebf6f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
@@ -0,0 +1,13 @@
+/* Test that we do not have ice when compile */
+/* { dg-do assemble } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */
+
+#include <riscv_vector.h>
+
+vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl)
+{
+ return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
