[Bug target/119644] __builtin_arm_set_fpscr ICE with -mgeneral-regs-only on Arm targets

2025-04-07 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119644 Richard Earnshaw changed: What|Removed |Added Keywords|ice-on-invalid-code |ice-on-valid-code --- Comment #4 fro

[Bug libstdc++/119550] cross compilation of libstdc++ fail for arm-none-eabi due to tzname tests

2025-03-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119550 --- Comment #4 from Richard Earnshaw --- At some point crosstool will run GCC's 'configure' script. What I need to see is the options it passes to that command. Sorry, I've never used crosstool, so I can't help with that. It is possible that

[Bug libstdc++/119550] cross compilation of libstdc++ fail for arm-none-eabi due to tzname tests

2025-03-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119550 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug rtl-optimization/115506] Possible but missed "cmp" instruction merging (x86 & ARM, optimization)

2025-03-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115506 --- Comment #4 from Richard Earnshaw --- (In reply to Uroš Bizjak from comment #2) > then RTL CSE2 pass would be able to merge: > > (insn 31 30 32 4 (set (reg:CCZ 17 flags) > (compare:CCZ (reg:QI 111 [ _30 ]) > (const_int -

[Bug testsuite/115827] [13/14/15 Regression] uninit-17.c no longer emits expected warning on arm soft-float

2025-03-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115827 --- Comment #7 from Richard Earnshaw --- (In reply to Richard Biener from comment #6) > IMO a testsuite issue then. Why would a missing warning from return f; /* { dg-warning "may be used" "unconditional" } */ be a testsuite issue?

[Bug middle-end/117811] [12/13/14/15 Regression] bad code for conditional right shift with autovec and neon since r12-897-gde56f95afaaa22

2025-03-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117811 Richard Earnshaw changed: What|Removed |Added Assignee|pinskia at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug middle-end/118939] [14/15 Regression] ada: executable segfaults on arm-linux-gnueabi when assigning an access to controlled type since r14-2653-g2971ff7b1d564a

2025-03-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118939 --- Comment #19 from Richard Earnshaw --- (In reply to Eric Botcazou from comment #18) > > So the real question is why has the size of the frame changed once it's too > > late to change the frame layout? > > The frame size has not changed, rath

[Bug middle-end/118939] [14/15 Regression] ada: executable segfaults on arm-linux-gnueabi when assigning an access to controlled type since r14-2653-g2971ff7b1d564a

2025-03-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118939 --- Comment #17 from Richard Earnshaw --- (In reply to Richard Earnshaw from comment #16) > That can't be right. If the frame size has changed, then the frame needs to > be laid out again and any earlier layout assumptions revisited. Here's a

[Bug middle-end/118939] [14/15 Regression] ada: executable segfaults on arm-linux-gnueabi when assigning an access to controlled type since r14-2653-g2971ff7b1d564a

2025-03-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118939 --- Comment #16 from Richard Earnshaw --- (In reply to Eric Botcazou from comment #13) > Possible kludge to work around the questionable mechanism: > > diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc > index 59b41e3d046..2d51874a05b

[Bug target/91614] [12/13/14 regression][arm] gcc.target/arm/unaligned-memcpy-2.c FAIL since r274986

2025-03-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91614 Richard Earnshaw changed: What|Removed |Added Summary|[12/13/14/15|[12/13/14 regression][arm]

[Bug middle-end/117811] [12/13/14/15 Regression] bad code for conditional right shift with autovec and neon since r12-897-gde56f95afaaa22

2025-03-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117811 --- Comment #21 from Richard Earnshaw --- Patch posted: https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678597.html

[Bug rtl-optimization/101995] [12/13/14/15 Regression] regression built-in memset missed-optimization arm -Os since r9-3594

2025-03-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101995 --- Comment #16 from Richard Earnshaw --- Still present. Perhaps more significantly (and possibly related) class x { public: x (); int func (); private: int a; }; int g () { x b; return b.func(); } generates: g(): push

[Bug target/119372] Aarch64: Compiling with -march=armv8-a+pauth -mbranch-protection=standard produces autiasp and retaa in the function epilogue

2025-03-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119372 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2025-03-19 Version|14.2.1

[Bug target/117931] gcc.target/arm/lp1243022.c fails since gcc-6-4265-g477ee35f511

2025-03-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117931 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/119196] New: Missed folding of vector comparisons

2025-03-10 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- c-c++-common/vector-compare-3.c contains the code: void g (T *x, T const *y, T *z, T *t) { *z = *x < *y | *x == *y; *t =

[Bug tree-optimization/119196] Missed folding of vector comparisons

2025-03-10 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119196 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/118942] [14/15 Only] vld1q_s{8,16}_x{3,4} use incorrect pointer type since they were added with r14-7202-gc8ec3e1327cb1e

2025-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118942 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug libgcc/117600] [15 regression] libgcc arm build doesn't respect --disable-werror

2025-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117600 --- Comment #2 from Richard Earnshaw --- libgcc should only be built with the current compiler, so I don't think it's unreasonable to expect -Werror to be always enabled.

[Bug rtl-optimization/119107] New: inconsistent elimination of redundant *_extend operations

2025-03-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- GCC often relies on combine to identify and eliminate redundant (zero|sign)_extend

[Bug debug/118221] gdb and objdump referencing functions that do not exist in binary

2025-02-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118221 --- Comment #10 from Richard Earnshaw --- Fixing this properly would require rewriting all of GCC's dwarf output code so that each function in a separate section had its own debug data (and perhaps using section groups to describe the relationsh

[Bug rtl-optimization/117712] [15 regression] ICE when building x265: internal compiler error: in expand_fix, at optabs.cc:5936 since r15-2890

2025-02-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117712 Richard Earnshaw changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug target/117525] [15 Regression] canvas.cc:1675:1: internal compiler error: in expand_fix, at optabs.cc:5952 since r15-2890

2025-02-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117525 --- Comment #19 from Richard Earnshaw --- I'm not convinced this is correct. See the discussion on the patch here: https://gcc.gnu.org/pipermail/gcc-patches/2003-March/098380.html and the related PR (https://gcc.gnu.org/bugzilla/show_bug.cgi?id

[Bug target/118089] [12/13/14/15 regression] arm thumb2 return sequence is suboptimal, especially at -O2

2025-02-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118089 --- Comment #4 from Richard Earnshaw --- Partially fixed. Still to do is implementing stack deallocation by using a POP of dead callee saved regs (for -Os).

[Bug rtl-optimization/116028] [15 Regression] gcc.dg/pr10474.c test failure since r15-1619-g3b9b8d6cfdf593

2025-02-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116028 --- Comment #13 from Richard Earnshaw --- (In reply to Surya Kumari Jangala from comment #3) > The parameter register is > saved in a volatile register which is saved on stack in the entry bb. > Instead, if the volatile register is saved just be

[Bug middle-end/118732] New: [15 regression] caller-saves optimization can inhibit shrink wrapping

2025-02-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
-optimization Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org CC: jskumari at gcc dot gnu.org, vmakarov at redhat dot com Target Milestone

[Bug target/118642] -specs=sync-none.specs doesn't work with LTO.

2025-01-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118642 Richard Earnshaw changed: What|Removed |Added Keywords||rejects-valid --- Comment #3 from Ri

[Bug target/118501] [14 regression] aarch64: ICE in simplify_context::simplify_subreg

2025-01-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501 --- Comment #14 from Richard Earnshaw --- (In reply to Matthias Klose from comment #13) > the backport requires some more work: > > ../../src/gcc/config/aarch64/aarch64.md:7255:13: error: > 'force_lowpart_subreg' was not declared in this scope;

[Bug target/118642] -specs=sync-none.specs doesn't work with LTO.

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
|1 Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org Status|UNCONFIRMED |NEW --- Comment #1 from Richard Earnshaw --- mine

[Bug target/118642] New: -specs=sync-none.specs doesn't work with LTO.

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
onent: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- Target: arm-none-eabi The arm-none-eabi port provides some alternative implementations of __sync_synchronize for different implementations of the archite

[Bug target/116448] gcc.target/arm/vfp-1.c uses the wrong instructions on Cortex-M55

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116448 --- Comment #5 from Richard Earnshaw --- If -fno-math-errno doesn't work, then we could consider moving those specific tests to a different file, with different optimization flags.

[Bug target/116448] gcc.target/arm/vfp-1.c uses the wrong instructions on Cortex-M55

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116448 --- Comment #4 from Richard Earnshaw --- (In reply to Torbjorn SVENSSON from comment #3) > Compiling the test case with -Os resolves the failed checks, but it also > starts failing on the sqrt() and sqrtf() calls. These are no longer expanded >

[Bug target/116448] gcc.target/arm/vfp-1.c uses the wrong instructions on Cortex-M55

2025-01-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116448 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/118564] DSP instruction support missing for ARM Cortex M4

2025-01-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118564 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRM

[Bug target/118460] [14/15 Regression] ICE on armv8.1-m.main with -mfloat-abi=hard

2025-01-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118460 --- Comment #6 from Richard Earnshaw --- Yes, that would work as a work-around. It's a bit of a hack though. The expectation is that we would use vsel for pretty much everything when it is available (particularly for fast-math), but we fail to

[Bug target/118460] [14/15 Regression] ICE on armv8.1-m.main with -mfloat-abi=hard

2025-01-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118460 --- Comment #4 from Richard Earnshaw --- arm_vsel_comparison_operator is rejecting the comparison (LT) because it is not one that the vsel instruction can handle. We should be reversing the order of operands to the compare instruction and then

[Bug lto/118136] Linking start code built with -flto with application where main signature does not match causes warning

2024-12-20 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118136 Richard Earnshaw changed: What|Removed |Added Resolution|INVALID |--- Last reconfirmed|

[Bug target/118089] [12/13/14/15 regression] arm thumb2 return sequence is suboptimal, especially at -O2

2024-12-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118089 --- Comment #1 from Richard Earnshaw --- > I suspect this is a consequence of moving to an rtl-based prologue. Or more accurately: epilogue. :)

[Bug target/118089] New: [12/13/14 regression] arm thumb2 return sequence is suboptimal, especially at -O2

2024-12-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Keywords: missed-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- Target: arm This is a regression that originally appeared in

[Bug target/118008] [14/15 regression] ICE when bootstrapping with Go on arm (gen_movdi, at config/arm/arm.md:6296)

2024-12-16 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118008 --- Comment #11 from Richard Earnshaw --- For the bare metal cross you probably need to configure with '--with-arch=armv7-a+fp --with-float-abi=hard' If that still doesn't trigger it, try adding '--with-mode=thumb'

[Bug target/116447] g++.dg/cpp23/ext-floating13.C fails on Cortex-M55 due to undefined reference

2024-12-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
, ||rearnsha at gcc dot gnu.org --- Comment #6 from Richard Earnshaw --- So I think this issue might be related to something Christophe and I were discussing the other day. The arm port defaults to not creating the type _fp16 by default, but on some CPUs this

[Bug target/117941] Partial backtrace on C++ exception on ARM

2024-12-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117941 --- Comment #5 from Richard Earnshaw --- > Is it then possible to have dwarf data on ARM in addition to the EABI defined > unwind section? I don't know, honesty, because I've not tried it. I'd be surprised if it worked though, at least, not wi

[Bug target/117941] Partial backtrace on C++ exception on ARM

2024-12-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117941 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116625] [15 regression] regressions on arm-eabi since r15-1619-g3b9b8d6cfdf593

2024-12-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116625 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116447] g++.dg/cpp23/ext-floating13.C fails on Cortex-M55 due to undefined reference

2024-12-02 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116447 --- Comment #1 from Richard Earnshaw --- How was the compiler configured and what's the full command line used when building the test?

[Bug target/117766] Confusion over whether ARM32 -march=armv8-a implies floating point support

2024-11-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117766 --- Comment #14 from Richard Earnshaw --- (In reply to Tom Lane from comment #13) > After further experimentation, it seems to me that: > > * There was a behavioral change between gcc 9.3.1 and the later releases I > tested. Specifically, in 9

[Bug target/114801] [14/15 Regression] arm: ICE in find_cached_value, at rtx-vector-builder.cc:100 with MVE intrinsics

2024-11-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114801 Richard Earnshaw changed: What|Removed |Added Keywords|ice-on-valid-code |ice-on-invalid-code --- Comment #40

[Bug testsuite/117419] test failures for enum-alias-{1,2,3} on arm-eabi

2024-11-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117419 --- Comment #4 from Richard Earnshaw --- enum size is ABI (affects data layout). So you can't use -f[no-]short-enums for executable tests. The best way to deal with this is to ensure that the size of the enum defaults to int (eg by adding a du

[Bug target/56513] Wrong code generation with -O3 on ARM

2024-11-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56513 --- Comment #8 from Richard Earnshaw --- For something this old, we should probably just close it as fixed as of Richi's patch.

[Bug target/114801] [14/15 Regression] arm: ICE in find_cached_value, at rtx-vector-builder.cc:100 with MVE intrinsics

2024-10-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114801 --- Comment #36 from Richard Earnshaw --- I've been looking at this. I think the real problem is that trunc_int_for mode is doing something incompatible with what the later code expects. We have /* Canonicalize BImode to 0 and STORE_FLAG_VA

[Bug target/116856] Generated Code with unaligned uint32_t potentially hardfaults on ARM (due to LDRD)

2024-09-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116856 --- Comment #8 from Richard Earnshaw --- BTW, rewriting the code as: #include typedef uint32_t __attribute__((aligned(1))) u32_u; void f() { static uint8_t array[64]; for (uint8_t i = 0; i < sizeof(array); i++) {

[Bug target/116856] Generated Code with unaligned uint32_t potentially hardfaults on ARM (due to LDRD)

2024-09-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116856 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|WAITING

[Bug target/116856] Generated Code with unaligned uint32_t potentially hardfaults on ARM (due to LDRD)

2024-09-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116856 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Ever confirmed|0

[Bug target/113780] [ARM] Incorrect indirect tailcall generated for PAC-enabled function.

2024-09-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113780 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |13.4

[Bug target/116597] [arm] indirect tailcalls with incomplete prototypes generate wrong code when using PACM

2024-09-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116597 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug target/116597] New: [arm] indirect tailcalls with incomplete prototypes generate wrong code when using PACM

2024-09-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Keywords: wrong-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- void (*f)(); // Or void (*f)(int, ...}; void g () { return f (1, 2, 3, 4

[Bug target/116517] ICE in arm_print_operand_address

2024-08-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116517 --- Comment #3 from Richard Earnshaw --- The invalid insn is created during late-combine.

[Bug target/116517] ICE in arm_print_operand_address

2024-08-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116517 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2024-08-28 Status|UNCONF

[Bug target/116329] no sibcalling for thumb1 (cortex-m0)

2024-08-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116329 Richard Earnshaw changed: What|Removed |Added Resolution|--- |WONTFIX Status|UNCONFIRM

[Bug rtl-optimization/86901] [AArch64] Suboptimal register allocation for int/float reinterpret

2024-07-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86901 --- Comment #4 from Richard Earnshaw --- But why not: f2: fmovw1, s0 ubfxw1, w1, 20, 11 cmp w1, 1015 bhi .L7 fmuls0, s0, s0 str s0, [x0] ret .L7: b g

[Bug target/96373] [11 Regression] SVE miscompilation on vectorized division loop, leading to FP exception

2024-07-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96373 --- Comment #25 from Richard Earnshaw --- (In reply to Kewen Lin from comment #24) > OK, thanks for the comments, I'll mark PR108977 as won't fix then. It would be more normal to mark it as fixed, but set the fix version to the earliest release

[Bug target/115611] mve: vsetq_lane for 64-bits has wrong codegen when setting lane 1

2024-07-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115611 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |11.5

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

2024-07-10 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090 --- Comment #9 from Richard Earnshaw --- It looks like the compiler now merges b into a rather than a into b. The result is the same, though and we don't need an lsr this way. Technically it ought to be better. But we do end up in a dance wit

[Bug target/103100] [11 Regression] unaligned access generated with memset or {} and -O2 -mstrict-align

2024-07-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103100 Richard Earnshaw changed: What|Removed |Added Target Milestone|11.5|12.5

[Bug c/115770] Undefined arm instruction (udf #255) is generated when optimizer is on O2

2024-07-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115770 --- Comment #2 from Richard Earnshaw --- Correction: the option to add is -fno-delete-null-pointer-checks Sorry for the confusion.

[Bug c/115770] Undefined arm instruction (udf #255) is generated when optimizer is on O2

2024-07-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115770 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/115732] Arm32 architecture definitions for v8+ appear to have wrong FPU/SIMD defaults

2024-07-02 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115732 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/115353] [14 regression] Missed thumb2 table branch instruction optimisations since r14-4946-g7006e5d2d7b5b2

2024-06-07 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115353 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |14.2

[Bug target/115360] cmse_nonsecure_call wrapper on arm missing STT_FUNCTION

2024-06-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/115353] [14/15 regression] Missed thumb2 table branch instruction optimisations since r14-4946-g7006e5d2d7b5b2

2024-06-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115353 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2024-06-05 Status|UNCONF

[Bug tree-optimization/115157] incorrect TBAA for derived types involving enum types

2024-06-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115157 --- Comment #4 from Richard Earnshaw --- The tests in the last patch fail on arm-eabi. The tests assume that sizeof(enum) == sizeof(int), which is not true if -fshort-enum is the default. + Chang

[Bug target/115086] bic is not used when the non-not part is a constant

2024-05-14 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115086 --- Comment #2 from Richard Earnshaw --- And perhaps more importantly the mov can even be hoisted outside of a loop.

[Bug target/115083] undefined reference for aarch64-w64-mingw32 target

2024-05-14 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115083 --- Comment #5 from Richard Earnshaw --- Please give the port developers time to finish working on the port. Only the initial patches have been pushed so far and there is plenty of work left to do.

[Bug target/115058] on target arm -mcpu=cortex-a78ae does not allow use pauth and dot product

2024-05-14 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115058 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|WAITING

[Bug target/115058] on target arm -mcpu=cortex-a78ae does not allow use pauth and dot product

2024-05-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115058 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-16 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #34 from Richard Earnshaw --- To be honest, I'm more concerned that we aren't eliminating a lot of these copies during the gimple optimization phase. The memcpy is really a type punning step (that's strictly ISO C compliant, rather

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-15 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #31 from Richard Earnshaw --- While that does seem to fix the bug, it's at the cost of 6 additional stores in the problematic test that are redundant other than changing the alias set view.

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #29 from Richard Earnshaw --- Sorry, I was looking at the wrong pair of insns. The earlier store to that location was insn 111. 111: [r212:SI (1 MEM[(struct Vec128 *)_179]+0 S4 A64)] = {r0:SI..r3:SI} It appears that the problem is

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #27 from Richard Earnshaw --- (In reply to Richard Earnshaw from comment #26) > (In reply to Richard Biener from comment #25) > > I think it's more interesting why > > > > * 119: [r216:SI (2 MEM[(struct Vec128 *)_179]+0 S4 A64)] = >

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #26 from Richard Earnshaw --- (In reply to Richard Biener from comment #25) > I think it's more interesting why > > * 119: [r216:SI (2 MEM[(struct Vec128 *)_179]+0 S4 A64)] = > {r0:SI..r3:SI} > > isn't considered as dependence? Wh

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #23 from Richard Earnshaw --- #0 ptr_deref_may_alias_decl_p (ptr=0x75e0c678, decl=0x75dff000) at /home/rearnsha/gnusrc/gcc-cross/gcc-13/gcc/tree-ssa-alias.cc:295 #1 0x01768173 in indirect_ref_may_alias_decl_p

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #22 from Richard Earnshaw --- (Previous analysis is based on gcc-13 branch)

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 Richard Earnshaw changed: What|Removed |Added CC||rguenth at gcc dot gnu.org --- Comme

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-04-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #20 from Richard Earnshaw --- Created attachment 57928 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57928&action=edit fully preprocessed testcase

[Bug target/111231] [12/13/14 regression] armhf: Miscompilation with -O2/-fno-exceptions level (-fno-tree-vectorize is working)

2024-03-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111231 --- Comment #19 from Richard Earnshaw --- This is another problem with (I suspect) incorrect aliasing information. If I compile with -fno-strict-aliasing, I get 88: f4432a1fvst1.8 {d18-d19}, [r3 :64] // {>E} SP+96/16 8c:

[Bug rtl-optimization/114338] (x & (-1 << y)) should be optimized to ((x >> y) << y) or vice versa

2024-03-14 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114338 --- Comment #1 from Richard Earnshaw --- Why would that be better? On a machine that does not lack registers, there's more instruction-level parallelism in (set (tmp) (-1)) (set (tmp) (ashift (tmp) (count))) (and (x) (x) (tmp)) What's more

[Bug target/114307] [ARM] GCC generates instruction that assembler rejects

2024-03-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307 --- Comment #2 from Richard Earnshaw --- Note that it's clear from the .syntax markers that this is inline assembler that's the source of the invalid instructions.

[Bug target/114307] [ARM] GCC generates instruction that assembler rejects

2024-03-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
|UNCONFIRMED |NEW Ever confirmed|0 |1 --- Comment #1 from Richard Earnshaw --- >From a full assembler dump: .syntax divided @ 71 "/home/rearnsha/gnusrc/gcc/master/gcc/testsuite/gcc.dg/vect/tree-vect.h" 1 vorr d6, d6

[Bug testsuite/113428] [14 regression] gcc.dg/gomp/bad-array-section-c-3.c fails after r14-7158-gb5476e4c881b0d

2024-03-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113428 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/113542] [14 Regression] gcc.target/arm/bics_3.c regression after change for pr111267

2024-03-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113542 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug testsuite/113428] [14 regression] gcc.dg/gomp/bad-array-section-c-3.c fails after r14-7158-gb5476e4c881b0d

2024-03-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113428 --- Comment #6 from Richard Earnshaw --- Patch here: https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647294.html

[Bug debug/100523] [11/12/13/14 Regression] armv8.1-m.main -fcompare-debug failure with -O -fmodulo-sched -mtune=cortex-a53

2024-03-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100523 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug libgcc/110775] [12/13/14 Regression] abort define causing issues in tsystem.h

2024-03-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110775 --- Comment #3 from Richard Earnshaw --- Perhaps we could use #define abort __builtin_trap ? A quick check seems to suggest this will work ok.

[Bug testsuite/113428] [14 regression] gcc.dg/gomp/bad-array-section-c-3.c fails after r14-7158-gb5476e4c881b0d

2024-03-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113428 --- Comment #4 from Richard Earnshaw --- /* { dg-warning {cast to pointer from integer of different size} "" { target *-*-* } .-2 } */ I'm guessing it's this that's causing the problem because int and int* are the same size on 32-bit targets.

[Bug testsuite/113428] [14 regression] gcc.dg/gomp/bad-array-section-c-3.c fails after r14-7158-gb5476e4c881b0d

2024-03-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113428 --- Comment #3 from Richard Earnshaw --- The referenced patch added the test that is failing. How is that a regression? Or are you suggesting that the test works without the rest of the patch applied?

[Bug target/113510] [14 Regression] [ARM Thumb] ICE in extract_constrain_insn with CPU cortex-m23

2024-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113510 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/113510] [14 Regression] [ARM Thumb] ICE in extract_constrain_insn with CPU cortex-m23

2024-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113510 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug testsuite/113611] [14 Regression] gcc.dg/pr110279-1.c fails on cross build since gcc-14-5779-g746344dd538

2024-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113611 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRM

[Bug target/112337] arm: ICE in arm_effective_regno when compiling for MVE

2024-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/112337] arm: ICE in arm_effective_regno when compiling for MVE

2024-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |14.0

[Bug middle-end/114136] wrong code for c23 fully anonymous arg lists on arm

2024-03-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114136 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Target Milestone|---

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