https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115506
--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #2)
> then RTL CSE2 pass would be able to merge:
>
> (insn 31 30 32 4 (set (reg:CCZ 17 flags)
> (compare:CCZ (reg:QI 111 [ _30 ])
> (const_int -32 [0xffffffffffffffe0]))) "pr115506.c":11:8 9
> {*cmpqi_1}
> (nil))
>
> and
>
> (insn 36 33 37 5 (set (reg:CC 17 flags)
> (compare:CC (reg:QI 111 [ _30 ])
> (const_int -33 [0xffffffffffffffdf]))) "pr115506.c":14:15 9
> {*cmpqi_1}
> (expr_list:REG_DEAD (reg:QI 111 [ _30 ])
> (nil)))
It's not that simple. Note that these two operations produce different results
in the logic of RTL.
The first generates reg:CCZ, the second generates reg:CC. So the generic
optimizers are not able to merge these operations as they are not the same. It
would require specific back-end knowledge to know if that could be done.
The other issue is that there is only one flags register. Extending its
lifetime is tricky as it could lead to impossible code if an instruction needed
to be inserted that clobbered the flags. It might not be needed in this
specific case, but there are cases where it can happen. Merging of flags is
best left until late in the optimization pipe, until we are sure that such
problems cannot occur.
