[Bug target/119100] RISC-V: missed opportunities for vector-scalar instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100 Paul-Antoine Arras changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/120459] RISC-V: redundant addi

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120459 --- Comment #4 from Paul-Antoine Arras --- Insn 2302 is folded into insn 1693 by apply_replacement() in haifa-sched.cc. But it is not clear to me at which point insn 2302 should be elided.

[Bug target/120459] New: RISC-V: redundant addi

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120459 Bug ID: 120459 Summary: RISC-V: redundant addi Product: gcc Version: 15.1.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assign

[Bug target/119361] RISC-V: x264 satd_4x4 stack spilling with mtune=generic-ooo for vls code but not on vla code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119361 Paul-Antoine Arras changed: What|Removed |Added CC||parras at gcc dot gnu.org --- Comm

[Bug target/120067] RISC-V: x264 sub4x4_dct high icount

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120067 Paul-Antoine Arras changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCON

[Bug target/120067] RISC-V: x264 sub4x4_dct high icount

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120067 --- Comment #3 from Paul-Antoine Arras --- (In reply to rdapp.gcc from comment #2) > There is indeed a problem with =zvl that we have been discussing in the > patchwork sync call for a while already. The issue is that we're handling > VLS > m

[Bug target/120067] New: RISC-V: x264 sub4x4_dct high icount

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120067 Bug ID: 120067 Summary: RISC-V: x264 sub4x4_dct high icount Product: gcc Version: 15.1.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/119373] RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 --- Comment #7 from Paul-Antoine Arras --- Created attachment 61176 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61176&action=edit RISC-V assembly with UF=2 This attachment shows the RISC-V assembly output with the unrolling factor manu

[Bug target/119373] RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 --- Comment #6 from Paul-Antoine Arras --- (In reply to Robin Dapp from comment #5) > > The analysis of SPEC2017's 510.parest_r shows that the topmost basic block > > is a tight loop (see attached reducer). Once vectorised, by unrolling and > >

[Bug fortran/119459] gfortran.dg/gomp/interop-5.f90 FAILs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119459 --- Comment #1 from Paul-Antoine Arras --- My mistake! This should now be fixed in commit e0a1d0e044c.

[Bug target/119373] RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 --- Comment #3 from Paul-Antoine Arras --- Comment on attachment 60822 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60822 Excerpt of the RISC-V assembly $ riscv64-linux-gnu-gcc -S -fverbose-asm -Ofast -mabi=lp64d -march=rv64gcv_zvl256b_

[Bug target/119373] RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 --- Comment #1 from Paul-Antoine Arras --- Created attachment 60821 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60821&action=edit Excerpt of the AArch64 assembly

[Bug target/119373] New: RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 Bug ID: 119373 Summary: RISC-V: missed unrolling opportunity Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/119373] RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 --- Comment #2 from Paul-Antoine Arras --- Created attachment 60822 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60822&action=edit Excerpt of the RISC-V assembly

[Bug target/119373] RISC-V: missed unrolling opportunity

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373 --- Comment #4 from Paul-Antoine Arras --- Comment on attachment 60821 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60821 Excerpt of the AArch64 assembly $ aarch64-linux-gnu-gcc -S -fverbose-asm -Ofast -mabi=lp64 -march=armv9-a+sve2 -ms

[Bug target/119100] RISC-V: missed opportunities for vector-scalar instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100 --- Comment #3 from Paul-Antoine Arras --- (In reply to Jeffrey A. Law from comment #2) > Paul -- have you run your patch on any design? And if so what did you run > and what was the performance delta before/after? Thanks for your input, Jeff!

[Bug target/119100] New: RISC-V: missed opportunities for vector-scalar instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100 Bug ID: 119100 Summary: RISC-V: missed opportunities for vector-scalar instructions Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal P

[Bug fortran/118714] [15 regression] SIGBUS in parse.cc:unexpected_eof

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118714 --- Comment #3 from Paul-Antoine Arras --- @Rainer, could you try with the patch I just committed, see if it actually fixes it for Solaris?

[Bug fortran/107067] New: [OpenMP] ICE with metadirective block statements

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107067 Bug ID: 107067 Summary: [OpenMP] ICE with metadirective block statements Product: gcc Version: 13.0 Status: UNCONFIRMED Keywords: openmp Severity: normal Prior