https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100
Bug ID: 119100
Summary: RISC-V: missed opportunities for vector-scalar
instructions
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: parras at gcc dot gnu.org
Target Milestone: ---
Created attachment 60645
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60645&action=edit
Source reduced from 554.roms
A number of RVV instructions have two variants: vector-vector and
vector-scalar. For instance, vfmadd.vv and vfmadd.vf: the latter accepts one
scalar operand.
However, SPEC2017's 554.roms shows that many opportunities of emitting the
vector-scalar variant are missed.
$ riscv64-linux-gnu-gfortran -S -Ofast -mabi=lp64d
-march=rv64gcv_zvl256b_zba_zbb_zbs_zicond -mrvv-vector-bits=zvl
rho_eos_tile.F90 -o rho_eos_tile.riscv64.s
$ cat rho_eos_tile.riscv64.s
...
(1) vfmv.v.f v6,fa0
vlse64.v v2,0(t0),s2
vmv.v.i v5,0
(2) vfmadd.vv v9,v6,v7
...
Here (1) and (2) could be combined into:
vfmadd.vf v9,fa0,v7
In RTL terms, it means combining:
(set (reg:RVVM1DF 516)
(vec_duplicate:RVVM1DF (reg:DF 517)))
into:
(set (reg:RVVM1DF 515)
(plus:RVVM1DF (mult:RVVM1DF (reg:RVVM1DF 362 [ vect_M.84_273.156 ])
(reg:RVVM1DF 516))
(reg:RVVM1DF 519)))
I have a draft patch dealing with the simple case where both instructions live
in the same basic block. However, the vec_duplicate often gets hoisted to the
loop preamble before reaching the combine pass.
