[Bug target/118945] RISC-V: VSETL pass: Don't promote Vectors ops from Tail agnostic to Tail Undisturbed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118945 Jeffrey A. Law changed: What|Removed |Added Assignee|vineetg at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/120553] Improve code to select between -1 and various values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120553 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/120404] RISC-V: inline asm FRM write over-written by FRM save/restore machinery

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120404 Jeffrey A. Law changed: What|Removed |Added Assignee|vineetg at gcc dot gnu.org |unassigned at gcc dot gnu.org

[Bug target/120479] missed opportunity to generate czero.nez

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120479 --- Comment #5 from Jeffrey A. Law --- Deferring indefinitely as I don't see a way to generate a czero right now due to the multiple use issues.

[Bug target/120603] Improve addition/subtraction on RISC-V for out of range constants

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120603 Jeffrey A. Law changed: What|Removed |Added CC||smunnangi1 at ventanamicro dot com --

[Bug target/120811] RISC-V: missed load offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 Jeffrey A. Law changed: What|Removed |Added CC||smunnangi1 at ventanamicro dot com --

[Bug target/121019] Explore removal of DI patterns for rv32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121019 --- Comment #1 from Jeffrey A. Law --- Per call today, deferring this idefinitely. If someone wants to pick it up, then by all means, please do. It's just not that high a priority.

[Bug target/120920] RISC-V: Possible optimization of bswap when zbb is enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120920 --- Comment #2 from Jeffrey A. Law --- Dusan posted a patch here, but I'm not convinced it's correct. Also note the patch failed its own test: https://patchwork.sourceware.org/project/gcc/patch/pr3pr08mb5738ed049e790435a3b5a8aebe...@pr3pr08mb5

[Bug target/121073] [16 Regression] RISC-V: ICE during RTL pass: avlprop insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121073 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-07-15 Ever confirmed|0

[Bug rtl-optimization/120242] [15 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/118241] RISC-V ICE: internal compiler error: in int_mode_for_mode, at stor-layout.cc:407 caused by prefetch instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118241 --- Comment #17 from Jeffrey A. Law --- The 4 patches in this space (two from me, two from Vineet) were backported to the gcc-15 branch.

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120356, which changed state. Bug 120356 Summary: [15 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 What|Removed

[Bug target/120356] [15 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120995, which changed state. Bug 120995 Summary: [15 regression] [RISC-V] ICE: unrecognizable insn UNSPEC_COMPARE_AND_SWAP with rv64gc_zabha_zacas https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120995 What

[Bug target/120995] [15 regression] [RISC-V] ICE: unrecognizable insn UNSPEC_COMPARE_AND_SWAP with rv64gc_zabha_zacas

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120995 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/121048] New: [16 Regression] Recent vectorizer changes cause RISC-V testsuite regressions

Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change is causing regressions on the RISC-V port: commit 4b47acfe2b626d1276e229a0cf165e934813df6c (HEAD

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 119267, which changed state. Bug 119267 Summary: RISC-V: gcc generates vsetivli with wrong LMUL with extended assembly https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119267 What|Removed

[Bug target/119267] RISC-V: gcc generates vsetivli with wrong LMUL with extended assembly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119267 Jeffrey A. Law changed: What|Removed |Added Status|SUSPENDED |RESOLVED Resolution|---

[Bug target/116363] gcc.c-torture/execute/conversion.c fails on H8/300

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116363 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/121019] New: Explore removal of DI patterns for rv32

: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- rv32 has 32bit GPRs, yet the port defines DI patterns. In the past that was commonplace to improve performance, but it can sometimes be harmful. So the goal is to evaluate if

[Bug target/109286] Assembler warnings about .init/.fini sections defined without attributes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109286 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120642 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/120995] [15 regression] [RISC-V] ICE: unrecognizable insn UNSPEC_COMPARE_AND_SWAP with rv64gc_zabha_zacas

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120995 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org Last

[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

|NEW Assignee|rdapp.gcc at gmail dot com |law at gcc dot gnu.org CC||majin at gcc dot gnu.org Last reconfirmed||2025-07-07 --- Comment #1 from Jeffrey A. Law --- So if I'm reading every

[Bug target/120920] RISC-V: Possible optimization of bswap when zbb is enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120920 --- Comment #1 from Jeffrey A. Law --- This looks fairly painful to capture in a backend pattern; I didn't see any particular attempt by combine that looked like a promising target pattern. I suspect you'll need to look at a simplify-rtx simpli

[Bug target/120922] [16 Regression] RISC-V: ICE during GIMPLE pass: vect in verify_range with -mrvv-max-lmul=m8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120922 Jeffrey A. Law changed: What|Removed |Added CC||tamar.christina at arm dot com --- Com

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116686] [15/16 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 116686, which changed state. Bug 116686 Summary: [15/16 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 What|Re

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 116686, which changed state. Bug 116686 Summary: [15/16 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 What|Re

[Bug target/119100] RISC-V: missed opportunities for vector-scalar instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100 --- Comment #10 from Jeffrey A. Law --- So I don't mind these changes being tagged to pr119100. My only concern is how do we know when we're done on this bug? We don't need to figure it out right now, but we do need to keep that question in mi

[Bug target/120922] [16 Regression] RISC-V: ICE during GIMPLE pass: vect in verify_range with -mrvv-max-lmul=m8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120922 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-07-07 Ever confirmed|0

[Bug target/120930] [16 Regression] RISC-V: Miscompile at -O[23] with zvl256b -mrvv-vector-bits=zvl since r16-1645-g309dbcea2ca

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120930 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-07-07 Ever confirmed|0

[Bug target/118886] Invalid fusions on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118886 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120550] [15 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/118057] RISC-V: Can't vectorize load and store with zvl128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118057 Jeffrey A. Law changed: What|Removed |Added Blocks|116242 | --- Comment #9 from Jeffrey A. Law -

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 118595, which changed state. Bug 118595 Summary: [15/16 regression] RISC-V: gfortran/c-interop test execution failures on RVV zvl > 128b since r15-3228-g771256bcb9d https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118595

[Bug target/118595] [15/16 regression] RISC-V: gfortran/c-interop test execution failures on RVV zvl > 128b since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118595 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/114665] [14/15 only] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120356] [15 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 --- Comment #8 from Jeffrey A. Law --- *** Bug 120651 has been marked as a duplicate of this bug. ***

[Bug target/120651] [15/16 Regression] RISC-V: Miscompile at -O3 with -flto since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120651 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120356] [15 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 Regression] RISC-V: |[15 Regression] RISC-V:

[Bug tree-optimization/120892] Missed unrolling at -O3 due to split-paths

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120892 --- Comment #3 from Jeffrey A. Law --- I think an argument could be made that split-paths should go away. It seemed like a reasonable idea at one time, but profitability was always marginal at best. I wouldn't lose any sleep if it went away.

[Bug rtl-optimization/120242] [15 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 regression] RISC-V: |[15 regression] RISC-V:

[Bug target/120242] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 --- Comment #5 from Jeffrey A. Law --- *** Bug 120627 has been marked as a duplicate of this bug. ***

[Bug target/120627] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-2186-g9d8ef2711df

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120627 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|ASSIGNED

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120659, which changed state. Bug 120659 Summary: ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:9879 with -O2 -mcpu=sifive-x280 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120659 What|Remo

[Bug target/120659] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:9879 with -O2 -mcpu=sifive-x280

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120659 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/119944] [16] RISC-V: g++.dg/torture/pr119610.C "terminate called after throwing an instance of 'int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119944 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|NEW

[Bug target/120714] RISC-V: incorrect frame pointer CFA address for stack-clash protection loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120714 Jeffrey A. Law changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #

[Bug target/120714] RISC-V: incorrect frame pointer CFA address for stack-clash protection loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120714 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120714, which changed state. Bug 120714 Summary: RISC-V: incorrect frame pointer CFA address for stack-clash protection loops https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120714 What|Removed

[Bug middle-end/120858] __builtin_rev_crc64_data64 poorly optimised when computing crc32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120858 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-06-29 Ever confirmed|0

[Bug middle-end/120855] New: [16 Regression] Recent changes causing ICE in assemble_name_resolve

Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit 0337e3c2743ca0c57da8c6b78b725a7d83f0b721 (HEAD) Author: Nathaniel Shead Date: Wed May 21 01:18:49 2025

[Bug sanitizer/119356] [15 Regression] libsanitizer fails to build on riscv musl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119356 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 regression] |[15 Regression] |lib

[Bug target/120714] RISC-V: incorrect frame pointer CFA address for stack-clash protection loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120714 Jeffrey A. Law changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug target/120811] RISC-V: missed load offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #4 from Jeffrey A. Law --- *** Bug 120459 has been marked as a duplicate of this bug. ***

[Bug target/120459] RISC-V: redundant addi

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120459 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRM

[Bug target/120811] RISC-V: missed load offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120828, which changed state. Bug 120828 Summary: [16 Regression] Unrecognized insn after recent RISC-V change for .vf support https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120828 What|Removed

[Bug target/120828] [16 Regression] Unrecognized insn after recent RISC-V change for .vf support

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120828 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120827] [15 Regression][RISC-V] ICE unrecognizible insn in LTO build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120827 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|WAITING

[Bug target/120827] [15 Regression][RISC-V] ICE unrecognizible insn in LTO build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120827 Jeffrey A. Law changed: What|Removed |Added Summary|[RISC-V] ICE unrecognizible |[15 Regression][RISC-V] ICE

[Bug target/120827] [RISC-V] ICE unrecognizible insn in LTO build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120827 --- Comment #6 from Jeffrey A. Law --- Odds are it's some split-code that isn't as safe as it should be. I can probably identify it if you can pass along the .split2 dump.

[Bug target/120828] New: [16 Regression] Unrecognized insn after recent RISC-V change for .vf support

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This is marginally reduced from rvv/base/bug-5.c. Compile with -O2 -march=rv64gcv -mabi=lp64d to trigger an unrecognized

[Bug target/120242] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 --- Comment #4 from Jeffrey A. Law --- *** Bug 120813 has been marked as a duplicate of this bug. ***

[Bug target/120813] [15/16 Regression] RISC-V: Miscompile at -O[23] since r15-9239

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120813 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120242] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 --- Comment #3 from Jeffrey A. Law --- Phew. After another debugging session I think this is ultimately an ext-dce bug. The promoted state on the key object is correct; the referenced patch just prevents the promoted state from being unnecessa

[Bug target/119007] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119007 --- Comment #3 from Jeffrey A. Law --- I think that's reasonable as well and one of the options discussed weeks ago in the patchwork call. I was thinking that having the relevant intrinsics set the flag was slightly better solution because it a

[Bug target/120811] RISC-V: missed load offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #2 from Jeffrey A. Law --- And combine. Though I suspect this is fallout from the way we're handling 2*simm12 cases with a define_insn_and_split. I've got a plan there and I'm just waiting for Shreya to wrap up her current task be

[Bug go/89173] FAIL: runtime/pprof

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89173 --- Comment #2 from Jeffrey A. Law --- Still happens on the BPI. But I think we have bigger issues to resolve, so deferring further action for now.

[Bug target/120356] [15/16 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |merzlyakovao at gcc dot gnu.org

[Bug target/86005] [RISCV] Invalid intermixing of __atomic_* libcalls and inline atomic instruction sequences

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005 --- Comment #12 from Jeffrey A. Law --- So this is probably still an issue given we're not supposed to use lock-free and locked sequences simultaneously on any given object. However, given this only affects us when we don't have the "A", c#2 and

[Bug target/104102] __builtin_frame_address(1) desn't work on riscv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104102 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug rtl-optimization/120795] [16 regression] ICE when building folly-2025.04.14.00 (df_refs_verify, at df-scan.cc:4029)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120795 --- Comment #5 from Jeffrey A. Law --- Thanks. Consider it pre-approved if it regtests. Or if you'd prefer I can do the submission steps... Thanks again for bisecting & testing.

[Bug rtl-optimization/120795] [16 regression] ICE when building folly-2025.04.14.00 (df_refs_verify, at df-scan.cc:4029)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120795 --- Comment #3 from Jeffrey A. Law --- It'd be a surprised if it's the ext-dce change, unless it's that second parameter to the remove_reg_equal_equiv_notes call. Looking at it again, I may have inverted the desired value. If bisection lands o

[Bug target/120651] [15/16 Regression] RISC-V: Miscompile at -O3 with -flto since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120651 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug target/119944] [16] RISC-V: g++.dg/torture/pr119610.C "terminate called after throwing an instance of 'int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119944 Jeffrey A. Law changed: What|Removed |Added CC||rzinsly at ventanamicro dot com --- Co

[Bug target/104102] __builtin_frame_address(1) desn't work on riscv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104102 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug target/119944] [16] RISC-V: g++.dg/torture/pr119610.C "terminate called after throwing an instance of 'int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119944 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-06-23 Ever confirmed|0

[Bug target/118595] [15/16 regression] RISC-V: gfortran/c-interop test execution failures on RVV zvl > 128b since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118595 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-06-23 Ever confirmed|0

[Bug target/109933] __atomic_test_and_set is broken for BIG ENDIAN riscv targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109933 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | Status|NEW

[Bug target/120782] RISC-V: vector-strict-align not working for spec17 521 ref size

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120782 --- Comment #4 from Jeffrey A. Law --- No strong opinion. I'll ponder pros/cons through the day and make a decision. You'll be able to either start your day tomorrow with it fixed or with the tuning knob patch installed.

[Bug target/120782] RISC-V: vector-strict-align not working for spec17 521 ref size

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120782 Jeffrey A. Law changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug go/89173] FAIL: runtime/pprof

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89173 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/119007] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119007 --- Comment #1 from Jeffrey A. Law --- I think when we discussed his several weeks ago the conclusion was this was a problem in the intrinsics space. Essentially the intrinsics can modify FRM and when they do they probably need to set -fno-roun

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-06-22 Depends on|

[Bug target/120763] New: [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- We want a way to track bugs to discuss during the weekly RISC-V GCC meeting. Keying that decision on the RISC-V keyword is far from

[Bug target/119830] RISC-V:Internal Compiler Error on RISC-V Windows Toolchain (32-bit program) with -march=rv64gc_zbb_zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119830 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug middle-end/44566] configuration with multiple targets / backends is not supported.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=44566 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550 --- Comment #6 from Jeffrey A. Law --- So this is an ext-dce bug, it just isn't obvious. ext-dce removes the extension in this insn: (insn 26 24 29 3 (set (reg:DI 141 [ pretmp_16 ]) (zero_extend:DI (subreg:QI (reg:DI 160) 0))) "j.c":8:

[Bug target/120736] [15/16 Regression] RISC-V: Miscompile at -O[23] since r15-5375-gbeec291225b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120736 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRM

[Bug target/118734] RISC-V: Vector broadcast via strided load.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118734 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/120627] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-2186-g9d8ef2711df

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120627 --- Comment #2 from Jeffrey A. Law --- *** Bug 120736 has been marked as a duplicate of this bug. ***

[Bug target/115759] RISC-V: complex code generated for lmbench's fwr when uses scalable autovec

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115759 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116504] wrong code with -mcpu=sifive-x280

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116504 --- Comment #8 from Jeffrey A. Law --- So for the record. Both testcases failed for me with QEMU. THe first case worked on real hardware while the second testcase failed on real hardware. I'm digging data out of an old email, so no clear indi

[Bug tree-optimization/116773] [meta-bug] TSVC missed optimizations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773 Bug 116773 depends on bug 113238, which changed state. Bug 113238 Summary: [14] RISC-V: gcc.dg vect-tsvc flakey test timeouts when under heavy workload https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113238 What|Removed

[Bug testsuite/113238] [14] RISC-V: gcc.dg vect-tsvc flakey test timeouts when under heavy workload

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113238 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED

[Bug target/113035] RISC-V: regression testsuite errors -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |WONTFIX Status|UNCONFIRMED

[Bug target/112531] [14] RISC-V: gcc.dg/unroll-8.c rtl-dump scan errors with --param=riscv-autovec-preference=scalable

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112531 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

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