https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120374
Bug ID: 120374
Summary: ext-dce fails to realize a shift pair makes bits dead
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
ext-dce may fail to realize that a shift pair that ultimately produces a zero
extended bitfield actually kills all the annoying upper bits. As a result it
may fail to eliminate prior extensions. This can be seen as an extraneous zero
extension in the code below once the 2nd step of the RISC-V logical AND
revamping is installed. Compile with -O2 -march=rv64gcb.
union gimple_statement_d;
typedef union gimple_statement_d *gimple;
enum br_predictor
{
END_PREDICTORS
};
enum prediction
{
NOT_TAKEN,
TAKEN
};
struct gimple_statement_base {
unsigned int subcode : 16;
unsigned num_ops;
};
union gimple_statement_d {
struct gimple_statement_base gsbase;
};
static inline void
gimple_predict_set_predictor (gimple gs, enum br_predictor predictor)
{
gs->gsbase.subcode = (gs->gsbase.subcode & (1 << 15))
| (unsigned) predictor;
}
static inline void
gimple_predict_set_outcome (gimple gs, enum prediction outcome)
{
if (outcome == TAKEN)
gs->gsbase.subcode |= (1 << 15);
else
gs->gsbase.subcode &= ~(1 << 15);
}
gimple stmt;
gimple
gimple_build_predict (enum br_predictor predictor, enum prediction outcome)
{
gimple_predict_set_predictor (stmt, predictor);
gimple_predict_set_outcome (stmt, outcome);
return stmt;
}
The zext.h instruction is redundant because the shifts immediately thereafter
wipe all those bits.
lui a5,%hi(stmt)
ld a4,%lo(stmt)(a5)
li a3,-32768
li a2,1
lhu a5,0(a4)
and a5,a5,a3
or a0,a0,a5
zext.h a0,a0
slli a5,a0,49
srli a5,a5,49
bne a1,a2,.L3
or a5,a0,a3
