https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120054
Jeffrey A. Law <law at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2025-05-04
Status|UNCONFIRMED |NEW
CC| |kito.cheng at gmail dot com
Ever confirmed|0 |1
--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Bisect lands on:
commit a992164c2899735525a7a267654473b7e527ef0d
Author: Jerry Zhang Jian <jerry.zhangj...@sifive.com>
Date: Wed Apr 30 15:34:07 2025 +0800
RISC-V: Fix missing implied Zicsr from Zve32x
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64im_zve32x
instead of rv64gc_zve32x to avoid Zicsr implied by g. Extra m is
added to avoid current 'V' extension requires 'M' extension
Signed-off-by: Jerry Zhang Jian <jerry.zhangj...@sifive.com>
