https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119706
--- Comment #11 from ktkachov at gcc dot gnu.org ---
(In reply to GCC Commits from comment #10)
> The releases/gcc-14 branch has been updated by Richard Biener
> :
>
> https://gcc.gnu.org/g:2bb4a431eace7e77562e686ecc9c9504045da003
>
> commit r1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119706
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Known to fail||15.0
Target Milestone|--
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119706
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Ever confirmed|0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119187
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119351
--- Comment #11 from ktkachov at gcc dot gnu.org ---
(In reply to Jakub Jelinek from comment #10)
> Has this worked in GCC 14? If so, has it been bisected what commit caused
> this (or made a bug no longer latent)?
Yes, it's g:68326d5d1a593dc0b
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119572
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97286
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119442
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Summary|[14/15 Regression] |[14 Regression] Regression
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119442
--- Comment #2 from ktkachov at gcc dot gnu.org ---
Patch at https://gcc.gnu.org/pipermail/gcc-patches/2025-March/679115.html
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119442
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Assigne
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119442
Bug ID: 119442
Summary: [14/15 Regression] Regression in creating SVE
predicate
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: aarch64-sve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119351
--- Comment #5 from ktkachov at gcc dot gnu.org ---
(In reply to Tamar Christina from comment #4)
> While looking at the codegen it looks like GROMACS has a lot of loops that
> get vectorized now and it's showing some inefficiencies in the codege
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119384
--- Comment #1 from ktkachov at gcc dot gnu.org ---
> We have a workload for aarch64 using the SIMDe translation error
Oops, this should say "SIMDe translation layer"
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119384
Bug ID: 119384
Summary: Extra move in tight loop with SIMD and subregs
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119351
--- Comment #1 from ktkachov at gcc dot gnu.org ---
> -DCMAKE_C_COMPILER=$COMPILERBIN -DCMAKE_CXX_COMPILER=$COMPILERXXBIN
$COMPILERBIN and $COMPILERXXBIN should point to the gcc and g++ executables
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119351
Bug ID: 119351
Summary: [15 Regression] Wrong code in GROMACS for AArch64
generic SVE VLS target
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: wrong
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119193
Bug ID: 119193
Summary: Suboptimal packing codegen
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
Priority: P3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119046
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolutio
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119046
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Assignee|unassigned at gcc dot gnu.org |ktkachov at gcc dot
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119046
--- Comment #2 from ktkachov at gcc dot gnu.org ---
(In reply to Tamar Christina from comment #1)
> The late-combine pass was supposed to handle these. probably worth a look
> into why it's not folding them in.
Yeah you're right. It turns out th
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119046
Bug ID: 119046
Summary: [15 Regression] Performance drop from not forming
lane-wise FMLAs with Eigen library
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Key
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119042
Bug ID: 119042
Summary: Optimize more !struct.x && !struct.y codegen cases
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: norma
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118976
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118151
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118974
Bug ID: 118974
Summary: Use SVE cbranch sequence for Neon modes when
TARGET_SVE
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118952
--- Comment #2 from ktkachov at gcc dot gnu.org ---
(In reply to Richard Sandiford from comment #1)
> I think this is essentially the same problem as PR34678.
Thanks, yeah I don't see PR34678 getting generally resolved any time soon. Is
there so
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118952
Bug ID: 118952
Summary: AArch64 get_fpcr and set_fpcr builtins don't block
reordering of operations past them
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Ke
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117978
--- Comment #4 from ktkachov at gcc dot gnu.org ---
(In reply to Richard Sandiford from comment #3)
> I think this would be better done in expand rather than gimple. The gimple
> representation would be a vector load in a 128-bit type, followed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118852
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118852
--- Comment #5 from ktkachov at gcc dot gnu.org ---
(In reply to Tamar Christina from comment #4)
> (In reply to ktkachov from comment #3)
> > FWIW I see this also on aarch64
>
> I filed the AArch64 bug weeks ago
> https://gcc.gnu.org/bugzilla/s
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118490
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Resolution|--- |FIXED
Status|A
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116445
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118490
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Assignee|unassigned at gcc dot gnu.org |soumyaa at gcc dot
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118490
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118377
--- Comment #8 from ktkachov at gcc dot gnu.org ---
(In reply to Tejas Belagod from comment #7)
> Sorry for the delay in replying. Though variable-length(VLA) SVE vector
> types behave as GNU vectors for C/C++ operator semantics, there is current
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118133
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117978
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117978
Bug ID: 117978
Summary: Optimise 128-bit-predicated SVE loads to Advanced SIMD
LDRs
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: aarch64-sve, misse
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117704
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117557
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117554
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117554
Bug ID: 117554
Summary: [15 Regression] ICE building 538.imagick_r with SVE
-msve-vector-bits=128
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: aarc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117499
Bug ID: 117499
Summary: [15 Regression] Segfault ICE building 511.povray_r
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117449
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Resolution|--- |FIXED
Status|A
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117449
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Last reconfirmed||2024-11-05
Target Milest
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117048
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolutio
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117344
Bug ID: 117344
Summary: Suboptimal use of movprfx in SVE intrinsics code
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: aarch64-sve, missed-optimization
Severi
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106329
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Assignee|prathamesh3492 at gcc dot gnu.org |unassigned at gcc do
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117093
--- Comment #4 from ktkachov at gcc dot gnu.org ---
(In reply to ktkachov from comment #3)
> If we remove the casts:
> uint32x4_t ror32_neon_tgt_gcc_bad(uint32x4_t r) {
> uint32x4_t a = r;
> uint32_t t;
> t = a[0]; a[0] = a[1]; a[1] =
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117093
--- Comment #3 from ktkachov at gcc dot gnu.org ---
I think it's the VIEW_CONVERT_EXPR that are hurting us (more complete dump
before expand):
_1 = VIEW_CONVERT_EXPR(r_3(D));
t_4 = BIT_FIELD_REF ;
a_5 = VEC_PERM_EXPR <_1, _1, { 1, 1, 2, 3 }
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117048
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|RESOLVED|ASSIGNED
Resolutio
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117093
Bug ID: 117093
Summary: Missing detection of REV64 vector permute
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117048
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Known to work||15.0
Resolution|--
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117050
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Last reconfirmed||2024-10-10
Ever confir
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117048
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Last reconfirmed||2024-10-09
Assig
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117048
--- Comment #1 from ktkachov at gcc dot gnu.org ---
Yeah, there is code in simplify-rtx.cc:3467 to simplify this pattern to a
rotate but it doesn't handle vector operands
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117048
Bug ID: 117048
Summary: Failure to combine into XAR instruction
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
P
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117013
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116999
--- Comment #1 from ktkachov at gcc dot gnu.org ---
This is inspired by the LLVM PR
https://github.com/llvm/llvm-project/pull/83
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116999
Bug ID: 116999
Summary: Fold SVE whilelt/le comparisons with max int value to
ptrue
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimizatio
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116934
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolutio
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116956
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
Summary|IC
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116934
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||saurabh.jha at arm dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116934
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116934
Bug ID: 116934
Summary: [15 Regression] ICE building 526.blender_r
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111733
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|NEW |ASSIGNED
--- Comment #3 fr
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116902
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
Summary|IC
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116902
Bug ID: 116902
Summary: ICE Another definition in block 43 follows the use
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116842
--- Comment #1 from ktkachov at gcc dot gnu.org ---
(In reply to ktkachov from comment #0)
> short a, b, c;
> unsigned d(unsigned, int e) { return e; }
> void f(bool g, short e[][3][3][3][3], unsigned h[][3][3], char i[][8],
>short j[][18
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116842
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116842
Bug ID: 116842
Summary: [15 Regression] ICE definition in block follows the
use
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116840
Bug ID: 116840
Summary: Optimise __builtin_parity for aarch64
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: enhancement
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116826
--- Comment #3 from ktkachov at gcc dot gnu.org ---
(In reply to Andrew Pinski from comment #2)
> Note PR 86710 lists the opposite (except without being a CST for the
> division).
>
> Just like PR 86710, this applies for log, log10 and log2 too
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116831
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
CC|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116831
Bug ID: 116831
Summary: [15 Regression] ICE with trunk mod vectorising for SVE
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: norma
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116815
--- Comment #2 from ktkachov at gcc dot gnu.org ---
(In reply to Andrew Pinski from comment #1)
> The easiest way to fix this is transform (late in gimple):
> _1 = a_2(D) + b_3(D);
> _5 = MAX_EXPR <_1, a_2(D)>;
>
> into:
> _tmp = .ADD_OVER
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116826
Bug ID: 116826
Summary: Optimise log (1.0 / x) into -log (x)
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: enhancement
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116819
--- Comment #4 from ktkachov at gcc dot gnu.org ---
(In reply to Andrew Pinski from comment #1)
> Note this code is undefined:
> prephitmp_52 = _44 ? _17 : _16(D);
>
> This is due to lifetime of the temp being bound for the call to second call
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116819
Bug ID: 116819
Summary: [15 Regression] ICE in vect_transform_stmt
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116812
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116815
Bug ID: 116815
Summary: Make better use of overflow flags in codegen of
min/max(a, add/sub(a, b))
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: miss
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116684
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Ever confirmed|0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57492
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Last reconfirmed|2013-05-31 00:00:00 |2024-9-11
C
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116630
Bug ID: 116630
Summary: Implement spaceshipm3 optab for aarch64
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: enhancement
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116569
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116628
--- Comment #2 from ktkachov at gcc dot gnu.org ---
(In reply to Andrew Pinski from comment #1)
> What revision/commit id are you using? Is it before or after r15-3411 ?
It's a fairly fresh g:6a1a856ba78589f7f5285b00ecd40ba2bbeef8b0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116628
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Known to work||14.2.0
Known to fail|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116628
Bug ID: 116628
Summary: [15 Regression] ICE in vect_analyze_loop_1 on aarch64
with -Ofast in TSVC
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: ice-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116569
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target Milestone|--- |15.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116569
Bug ID: 116569
Summary: [15 Regression] ICE in to_constant, at poly-int.h:592
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: aarch64-sve, ice-on-valid-code
Sev
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63521
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NE
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116564
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Ever confirmed|0 |1
Target|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116541
Bug ID: 116541
Summary: [14/15 Regression] Inefficient missing use of reg+reg
addressing modes
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114063
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116509
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Ever confirmed|0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Summary|[15 Regression] ICE |[12/13/14/15 Regression]
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
CC||rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116391
Bug ID: 116391
Summary: Emit spellcheck suggestions for __arm_rsr and
__arm_wsr intrinsics
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: diagnostic
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116367
Bug ID: 116367
Summary: Handle vector shuffles better
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
Priority: P
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