[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

2024-07-09 Thread jordi.sala at semidynamics dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 --- Comment #8 from Jordi Sala --- (In reply to JuzheZhong from comment #7) > (In reply to Jordi Sala from comment #6) > > Perfect, that's what I was looking for. I'm thinking of adding a way to tell > > GCC to minimize, maximize or preserve SEW

[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

2024-07-08 Thread jordi.sala at semidynamics dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 --- Comment #6 from Jordi Sala --- Perfect, that's what I was looking for. I'm thinking of adding a way to tell GCC to minimize, maximize or preserve SEW on vsetvl expand. Like -mrvv-vsetvl-sew={maximize,minimize,preserve}

[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

2024-07-08 Thread jordi.sala at semidynamics dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 --- Comment #4 from Jordi Sala --- problem is this is not related to the vectorizer as far as I'm aware, so setting -mrvv-max-lmul=m8 does not change the fact that vsetvl pass is going to change the loads and stores from m8 to m2

[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

2024-07-08 Thread jordi.sala at semidynamics dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 --- Comment #2 from Jordi Sala --- Thanks, is it possible to force a bigger LMUL currently? It's mainly for performance reasons.

[Bug target/115795] New: RISC-V: vsetvl step causes wrong codegen after fusing info

2024-07-05 Thread jordi.sala at semidynamics dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 Bug ID: 115795 Summary: RISC-V: vsetvl step causes wrong codegen after fusing info Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Pr