[Bug target/115093] New: RISC-V Vector ICE in extract_insn: unrecognizable insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115093 Bug ID: 115093 Summary: RISC-V Vector ICE in extract_insn: unrecognizable insn Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug target/112651] RISC-V Vector new option -mvect-lmul required to force LMUL values (rather than --param=riscv-autovec-lmul to hint at values)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112651 Jeremy Bennett changed: What|Removed |Added Summary|RISC-V Vector |RISC-V Vector new option

[Bug target/112648] RISC-V Vector parameter riscv-autovec-lmul value is ineffective

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648 --- Comment #3 from Jeremy Bennett --- Following a discussion on the weekly call, it seems that I have misunderstood the purpose of this parameter. It seems it is a hint to the optimizer that a particular LMUL value is most efficient, not as a m

[Bug target/112648] RISC-V Vector parameter riscv-autovec-lmul value is ineffective

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648 --- Comment #2 from Jeremy Bennett --- Thanks Richard. Bug 112651 filed to capture this suggestion.

[Bug target/112651] New: RISC-V Vector --param=riscv-autovec-lmul should be -mvect-lmul

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112651 Bug ID: 112651 Summary: RISC-V Vector --param=riscv-autovec-lmul should be -mvect-lmul Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug other/112650] New: RISC-V parameters are not documented

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112650 Bug ID: 112650 Summary: RISC-V parameters are not documented Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: other

[Bug target/112648] New: RISC-V Vector parameter riscv-autovec-lmul value is ineffective

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648 Bug ID: 112648 Summary: RISC-V Vector parameter riscv-autovec-lmul value is ineffective Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/111548] RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548 Jeremy Bennett changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug middle-end/111566] New: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 Bug ID: 111566 Summary: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/111548] New: RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548 Bug ID: 111548 Summary: RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal P

[Bug middle-end/111395] RISC-V Vector Fortran: ICE in get_avl_or_vl_reg (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/111391] RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/111395] New: RISC-V Vector Fortran: ICE in get_avl_or_vl_reg (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 Bug ID: 111395 Summary: RISC-V Vector Fortran: ICE in get_avl_or_vl_reg (vsetvl pass) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/111391] New: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391 Bug ID: 111391 Summary: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 Jeremy Bennett changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 --- Comment #2 from Jeremy Bennett --- (In reply to JuzheZhong from comment #1) > I can't reproduce the ICE in your testcase with same command. > > ~/work/toolchain/develop/build/dev-rv64gcv_zfh-lp64d-medany-linux-spike/ > install/bin/riscv64-u

[Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 Bug ID: 111375 Summary: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296 Jeremy Bennett changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/111295] RISC-V vector ICE in vsetvl pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/111295] RISC-V vector ICE in vsetvl pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295 --- Comment #4 from Jeremy Bennett --- @JuzheZhong - it's a C test case, not C++. Look like you are trying to compile it as C++.

[Bug target/111295] RISC-V vector ICE in vsetvl pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295 --- Comment #1 from Jeremy Bennett --- Further analysis suggests this also causes the following SPEC CPU 2017 benchmarks to fail: 602.gcc_s, 648.exchange2_s, 607.cactuBSSN_s, 621.wrf_s, 627.cam4_s, 628.pop2_s, 638.imagick_s, 649.fotonik3d_s and

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296 --- Comment #1 from Jeremy Bennett --- Created attachment 55844 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55844&action=edit Testcase (test.cpp)

[Bug middle-end/111296] New: RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296 Bug ID: 111296 Summary: RISC-V vector: ICE in lra_split_hard_reg_for during reload pass Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/111295] New: RISC-V vector ICE in vsetvl pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295 Bug ID: 111295 Summary: RISC-V vector ICE in vsetvl pass Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end

[Bug fortran/110996] RISC-V vector Fortran: SEGV ICE during parsing

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110996 --- Comment #3 from Jeremy Bennett --- @JuzheZhong I believe this is in someway related to RVV. If I remove `v' from the march: riscv64-unknown-linux-gnu-gfortran -march=rv64gc -mabi=lp64d -c -Ofast testcase.f90 The output I get is correc

[Bug middle-end/110994] RISC-V Fortran: Illegal instruction ICE with scalable autovec

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/110989] RISC-V vector ICE due to invalid tree code in GIMPLE vect pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110989 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/110964] RISC-V vector ICE in expand_cond_len_ternop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110964 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/110962] RISC-V vector Fortran ICE in expand_expr_real_2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110962 Jeremy Bennett changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/110950] RISC-V vector ICE in expand_const_vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950 Jeremy Bennett changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug fortran/110996] New: RISC-V vector Fortran: SEGV ICE during parsing

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110996 Bug ID: 110996 Summary: RISC-V vector Fortran: SEGV ICE during parsing Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: f

[Bug middle-end/110994] New: RISC-V Fortran: Illegal instruction ICE with scalable autovec

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 Bug ID: 110994 Summary: RISC-V Fortran: Illegal instruction ICE with scalable autovec Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/110989] New: RISC-V vector ICE due to invalid tree code in GIMPLE vect pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110989 Bug ID: 110989 Summary: RISC-V vector ICE due to invalid tree code in GIMPLE vect pass Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/110964] New: RISC-V vector ICE in expand_cond_len_ternop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110964 Bug ID: 110964 Summary: RISC-V vector ICE in expand_cond_len_ternop Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: midd

[Bug middle-end/110962] New: RISC-V vector Fortran ICE in expand_expr_real_2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110962 Bug ID: 110962 Summary: RISC-V vector Fortran ICE in expand_expr_real_2 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug middle-end/110950] RISC-V vector ICE in expand_const_vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950 --- Comment #1 from Jeremy Bennett --- Created attachment 55709 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55709&action=edit Script to run the compilation

[Bug middle-end/110950] New: RISC-V vector ICE in expand_const_vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950 Bug ID: 110950 Summary: RISC-V vector ICE in expand_const_vector Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-