[Bug target/119944] New: [16] RISC-V:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119944 Bug ID: 119944 Summary: [16] RISC-V: Product: gcc Version: 16.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassign

[Bug target/119944] [16] RISC-V: g++.dg/torture/pr119610.C "terminate called after throwing an instance of 'int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119944 Edwin Lu changed: What|Removed |Added Summary|[16] RISC-V:|[16] RISC-V: |

[Bug c++/119930] [16 regression] g++.dg/coroutines/torture/pr103953.C FAILs with -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119930 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #1) > I noticed this too. It was working at r16-89-g0650ea627399a0 . for risc-v, our postcommit has it starting within this range https://github.com/gcc-mirror/gcc/compa

[Bug target/119942] New: [16 Regression] RISC-V: Segmentation fault in pr103953.exe

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119942 Bug ID: 119942 Summary: [16 Regression] RISC-V: Segmentation fault in pr103953.exe Product: gcc Version: 16.0 Status: UNCONFIRMED Severity: normal Pr

[Bug target/119865] New: [15/16 regression] RISC-V: ICE in g++.target/riscv/mv(c)-symbols[1-5].C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119865 Bug ID: 119865 Summary: [15/16 regression] RISC-V: ICE in g++.target/riscv/mv(c)-symbols[1-5].C Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/119672] [15 regression] RISC-V: ICE during RTL pass: cse1 in as_a, at machmode.h:391

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119672 --- Comment #11 from Edwin Lu --- (In reply to Robin Dapp from comment #8) > (In reply to Jakub Jelinek from comment #7) > > Thanks, I've posted it to gcc-patches in case some CI picks it up too: > > https://gcc.gnu.org/pipermail/gcc-patches/202

[Bug target/119672] New: [15 regression] RISC-V: ICE during RTL pass: cse1 in as_a, at machmode.h:391

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119672 Bug ID: 119672 Summary: [15 regression] RISC-V: ICE during RTL pass: cse1 in as_a, at machmode.h:391 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: n

[Bug target/119598] New: [15 regression] RISC-V: pr119114.c -O3 -ftree-vectorize execution test since r15-9062-g70391e3958d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119598 Bug ID: 119598 Summary: [15 regression] RISC-V: pr119114.c -O3 -ftree-vectorize execution test since r15-9062-g70391e3958d Product: gcc Version: 15.0

[Bug libgomp/119559] New: [15 regression] GOMP: ICE in modify_call_for_omp_dispatch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119559 Bug ID: 119559 Summary: [15 regression] GOMP: ICE in modify_call_for_omp_dispatch Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Pri

[Bug target/119361] RISC-V: x264 satd_4x4 stack spilling with mtune=generic-ooo for vls code but not on vla code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119361 --- Comment #3 from Edwin Lu --- (In reply to Robin Dapp from comment #2) > I looked into this some more and it points to a general deficiency in how we > handle the split between VLA and VLS modes. > With ...bits=zvl the RVVM1SI etc modes. beco

[Bug target/113076] [14] RISC-V: gfortran.dg/dec_io_1.f90 runtime error after r14-4972-g8aa47713701

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113076 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/119361] New: RISC-V: x264 satd_4x4 stack spilling with mtune=generic-ooo for vls code but not on vla code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119361 Bug ID: 119361 Summary: RISC-V: x264 satd_4x4 stack spilling with mtune=generic-ooo for vls code but not on vla code Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/119228] New: [15 regression] RISC-V: ICE in c-c++-common/attr-nonstring-6/14.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119228 Bug ID: 119228 Summary: [15 regression] RISC-V: ICE in c-c++-common/attr-nonstring-6/14.c Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/119115] [15 regression] RISC-V: miscompile at -O3 with zvl256b -fsigned-char -fwrapv since r15-1579-g792f97b44ff

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119115 --- Comment #4 from Edwin Lu --- (In reply to Robin Dapp from comment #3) > Ah Edwin, would you mind CC'ing on such regressions? Thanks. my bad. will do that for future regressions

[Bug target/119115] New: [15 regression] RISC-V: miscompile at -O3 with zvl256b -fsigned-char -fwrapv since r15-1579-g792f97b44ff

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119115 Bug ID: 119115 Summary: [15 regression] RISC-V: miscompile at -O3 with zvl256b -fsigned-char -fwrapv since r15-1579-g792f97b44ff Product: gcc Version: 15.0 Status: UNCON

[Bug target/119114] New: [14/15 regression] RISC-V: miscompile at -O3 since r14-4077-g86451305d8b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119114 Bug ID: 119114 Summary: [14/15 regression] RISC-V: miscompile at -O3 since r14-4077-g86451305d8b Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug target/116686] [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 --- Comment #8 from Edwin Lu --- (In reply to Robin Dapp from comment #7) > Hmm, I don't fully understand. We're actually building with zvl256b right, > zvl1024b is first and thus gets overridden? But with zvl256b and QEMU > vlen=256 I'm not s

[Bug target/118950] New: [14/15 regression] RISC-V: rv64gcv runtime mismatch at -O3 since r14-4038-gb975c0dc3be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118950 Bug ID: 118950 Summary: [14/15 regression] RISC-V: rv64gcv runtime mismatch at -O3 since r14-4038-gb975c0dc3be Product: gcc Version: 15.0 Status: UNCONFIRMED S

[Bug target/118931] New: [15] RISC-V: rv64gcv miscompile at -O[23] since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118931 Bug ID: 118931 Summary: [15] RISC-V: rv64gcv miscompile at -O[23] since r15-3228-g771256bcb9d Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/117974] RISC-V: VSETVL hoisting across branch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117974 --- Comment #9 from Edwin Lu --- After talking with Palmer a bit about this, it looks like there might be an issue with regards to insn scheduler. With -fno-schedule-insns the vsetvl is inserted after the branch instead of before https://godbolt

[Bug target/118840] New: RISC-V: current rv64gcv testsuite failures as of r15-7464-g30a3a557a54

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118840 Bug ID: 118840 Summary: RISC-V: current rv64gcv testsuite failures as of r15-7464-g30a3a557a54 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/118595] [15 regression] RISC-V: gfortran/c-interop test execution failures on RVV zvl > 128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118595 --- Comment #1 from Edwin Lu --- bisected to r15-3228-g771256bcb9d as the first bad commit

[Bug target/118601] New: [15] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118601 Bug ID: 118601 Summary: [15] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets Product: gcc Version: 15.0 Status: UNCONFIRMED Severit

[Bug target/118595] New: [15 regression] RISC-V: gfortran/c-interop test execution failures on RVV zvl > 128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118595 Bug ID: 118595 Summary: [15 regression] RISC-V: gfortran/c-interop test execution failures on RVV zvl > 128b Product: gcc Version: 15.0 Status: UNCONFIRMED Sev

[Bug target/118119] [15 regression] RISC-V: gcc.c-torture/execute/va-arg-24.c zvl256b failure

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118119 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug tree-optimization/118405] [15 regression] RISC-V: ICE in verify_gimple during GIMPLE pass vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118405 --- Comment #1 from Edwin Lu --- >From my tinkering with the code, I've only really been able to bypass the added check as a potential "solution". For example, something like this essentially keeps the guaranteed `ltype = vectype` update regardl

[Bug tree-optimization/118405] New: [15 regression] RISC-V: ICE in verify_gimple during GIMPLE pass vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118405 Bug ID: 118405 Summary: [15 regression] RISC-V: ICE in verify_gimple during GIMPLE pass vect Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/118363] [15 regression] RISC-V: excess errors in c-c++-common/gomp/dispatch-11.c with zvls > 128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118363 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/118363] New: [15 regression] RISC-V: excess errors in c-c++-common/gomp/dispatch-11.c with zvls > 128

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118363 Bug ID: 118363 Summary: [15 regression] RISC-V: excess errors in c-c++-common/gomp/dispatch-11.c with zvls > 128 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/118119] New: [15 regression] RISC-V: gcc.c-torture/execute/va-arg-24.c zvl256b failure

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118119 Bug ID: 118119 Summary: [15 regression] RISC-V: gcc.c-torture/execute/va-arg-24.c zvl256b failure Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norm

[Bug target/118036] [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-1[12].c abort

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118036 Edwin Lu changed: What|Removed |Added CC||rdapp at gcc dot gnu.org Summary|

[Bug target/118036] New: [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-11.c abort

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118036 Bug ID: 118036 Summary: [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-11.c abort Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/117970] [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 --- Comment #5 from Edwin Lu --- this testcase also appears to be flakey for these three targets: - rv32imac-ilp32d - rv64imac-lp64d - rv64imc_zicsr_zifencei-lp64d https://github.com/patrick-rivos/gcc-postcommit-ci/issues/2237 https://github.co

[Bug target/117991] New: [15] RISC-V: g++/template/builtin-speculation-overloads[14].C assertion error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117991 Bug ID: 117991 Summary: [15] RISC-V: g++/template/builtin-speculation-overloads[14].C assertion error Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/117970] [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 --- Comment #4 from Edwin Lu --- (In reply to Lewis Hyatt from comment #2) > Thanks, I will see what I can find. Did you, by any chance, run the tests > before/after r15-6016 in the same build directory? I think this error would > make sense to

[Bug target/117970] [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 --- Comment #1 from Edwin Lu --- (In reply to Edwin Lu from comment #0) > Our postcommit ci is seeing the following regressions: > > FAIL: g++.dg/modules/xtreme-header-7_b.C -std=c++2b (test for excess errors) > FAIL: g++.dg/modules/xtreme-head

[Bug target/117970] New: [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 Bug ID: 117970 Summary: [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data Product: gcc Version: 15.0 Status: UNCONFIRMED Seve

[Bug target/117906] New: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-5897-g31250baf814

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117906 Bug ID: 117906 Summary: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-5897-g31250baf814 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/117771] [15 Regression] RISC-V: stage1 fails to build using gcc-9.4 since r15-5603-gb3f1b9e2aa0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117771 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #2) > Created attachment 59699 [details] > Patch to test > > Can you test this patch? It moves the include of sstream above safe-ctype.h. > I don't know why it worked befo

[Bug target/117771] New: [9 Regression] RISC-V: stage1 fails to build using gcc-9.5 since r15-5603-gb3f1b9e2aa0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117771 Bug ID: 117771 Summary: [9 Regression] RISC-V: stage1 fails to build using gcc-9.5 since r15-5603-gb3f1b9e2aa0 Product: gcc Version: 9.5.0 Status: UNCONFIRMED

[Bug bootstrap/117407] [15 regression] bootstrap fails after r15-4847-g79a75b1f551821

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117407 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #2 from

[Bug libbacktrace/117413] [15 regression] RISC-V: stage2 build failure with __builtin_prefetch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117413 Edwin Lu changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRMED

[Bug libbacktrace/117413] New: [15 regression] RISC-V: stage2 build failure with __builtin_prefetch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117413 Bug ID: 117413 Summary: [15 regression] RISC-V: stage2 build failure with __builtin_prefetch Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/114175] [13/14] Execution test failures on gcc.dg/c23-stdarg-6.c on multiple targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/116959] [15 regression] RISC-V: more ICEs in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116959 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/116822] [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug testsuite/117250] [15] RISC-V: gfortran.dg/unsigned_38.f90 Error: Operand of unary numeric operator '-' at (1) is UNSIGNED(4)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117250 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug testsuite/117250] New: [15] RISC-V: gfortran.dg/unsigned_38.f90 Error: Operand of unary numeric operator '-' at (1) is UNSIGNED(4)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117250 Bug ID: 117250 Summary: [15] RISC-V: gfortran.dg/unsigned_38.f90 Error: Operand of unary numeric operator '-' at (1) is UNSIGNED(4) Product: gcc Version: 15.0

[Bug target/117177] New: [15 regression] RISC-V: Error when building glibc from source since r15-4377-gf9bac238840

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117177 Bug ID: 117177 Summary: [15 regression] RISC-V: Error when building glibc from source since r15-4377-gf9bac238840 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug tree-optimization/117140] [15 regression] RISC-V: ICE in initialize_flags_in_bb for rv32gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117140 --- Comment #3 from Edwin Lu --- Created attachment 59349 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59349&action=edit reduced testcase (In reply to Andrew Pinski from comment #2) > I suspect r15-4324-gaccb85345edb91 . Confirmed to b

[Bug target/117140] New: [15 regression] RISC-V: ICE in initialize_flags_in_bb for rv32gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117140 Bug ID: 117140 Summary: [15 regression] RISC-V: ICE in initialize_flags_in_bb for rv32gcv Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116959] [15 regression] RISC-V: more ICEs in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116959 --- Comment #1 from Edwin Lu --- Created attachment 59279 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59279&action=edit vwsll-run.i

[Bug target/116959] New: [15 regression] RISC-V: more ICEs in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116959 Bug ID: 116959 Summary: [15 regression] RISC-V: more ICEs in compute_nregs_for_mode Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal P

[Bug target/116822] [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 Edwin Lu changed: What|Removed |Added CC||rguenth at gcc dot gnu.org --- Comment #2 fr

[Bug target/116822] [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 --- Comment #1 from Edwin Lu --- Bisected down to r15-3794-g2c04f175de4 as the first bad commit

[Bug target/116822] New: [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 Bug ID: 116822 Summary: [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug tree-optimization/116820] [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c since r15-3768-g4150bcd205e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116820 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116820] [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c since r15-3768-g4150bcd205e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116820 Edwin Lu changed: What|Removed |Added Summary|[15 regression] RISC-V: ICE |[15 regression] RISC-V: ICE

[Bug target/116686] [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 --- Comment #5 from Edwin Lu --- Created attachment 59183 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59183&action=edit tree output Here's the tree output

[Bug target/116686] [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 --- Comment #4 from Edwin Lu --- Created attachment 59182 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59182&action=edit verbose output Here's the verbose output

[Bug target/116820] New: [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116820 Bug ID: 116820 Summary: [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c Product: gcc Version: 15.0 Status: UNCONFIRMED Severi

[Bug target/116686] New: [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 Bug ID: 116686 Summary: [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2 Product: gcc Version: 15.0 Status

[Bug target/116685] RISC-V: missed optimization on vector dot products

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116685 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #1) > -fno-vect-cost-model fixes some of these. I hadn't taken a look with -fno-vect-cost-model until now but it seems like there's some weird codegen with the 3 element d

[Bug fortran/116661] Undefined behavior when compiling interop-1.f90 gomp test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116661 --- Comment #5 from Edwin Lu --- (In reply to Thomas Schwinge from comment #4) > (In reply to GCC Commits from comment #3) > > commit r15-3581-g4e9265a474def98cb6cdb59c15fbcb7630ba330e > > Author: Tobias Burnus > > Date: Wed Sep 11 09:25:47 2

[Bug other/116685] New: RISC-V: missed optimization on vector dot products

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116685 Bug ID: 116685 Summary: RISC-V: missed optimization on vector dot products Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Componen

[Bug testsuite/116536] New: [15 Regression] gcc.dg/ipa/ipa-icf-38.c: error executing dg-final since r15-3254-g3f51f0dc88e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116536 Bug ID: 116536 Summary: [15 Regression] gcc.dg/ipa/ipa-icf-38.c: error executing dg-final since r15-3254-g3f51f0dc88e Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug libfortran/105361] Incorrect end-of-file condition for derived-type I/O

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105361 --- Comment #17 from Edwin Lu --- (In reply to Jerry DeLisle from comment #16) > Created attachment 58799 [details] > Revised test case with careful precision and tolerance values. > > New suggested test case which passes on x86-64-linux. We r

[Bug target/116425] New: RISC-V missed optimization: vector lowering along lmul boundaries

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116425 Bug ID: 116425 Summary: RISC-V missed optimization: vector lowering along lmul boundaries Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/115862] [15 Regression] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862 Edwin Lu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 115862, which changed state. Bug 115862 Summary: [15 Regression] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862 What|Removed

[Bug target/116303] New: RISC-V: -mcpu doesn't populate .attribute arch string when directly invoking cc1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116303 Bug ID: 116303 Summary: RISC-V: -mcpu doesn't populate .attribute arch string when directly invoking cc1 Product: gcc Version: 15.0 Status: UNCONFIRMED Severit

[Bug target/116273] New: [14/15 regression] RISC-V: gcc.dg/long_branch.c flakey timeout

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116273 Bug ID: 116273 Summary: [14/15 regression] RISC-V: gcc.dg/long_branch.c flakey timeout Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116261] New: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-2739-g4cb07a38233

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116261 Bug ID: 116261 Summary: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-2739-g4cb07a38233 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug fortran/116255] New: [15 only] RISC-V: STOP 12 execution error on gfortran.dg/class_transformational_2.f90

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116255 Bug ID: 116255 Summary: [15 only] RISC-V: STOP 12 execution error on gfortran.dg/class_transformational_2.f90 Product: gcc Version: 15.0 Status: UNCONFIRMED Se

[Bug libstdc++/116247] New: [15] RISC-V: shared_ptr_atomic.h: uintptr_t not declared in scope

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116247 Bug ID: 116247 Summary: [15] RISC-V: shared_ptr_atomic.h: uintptr_t not declared in scope Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/113578] Incorrect sign printed for -nan on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113578 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #12 fro

[Bug libfortran/105361] Incorrect end-of-file condition for derived-type I/O

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105361 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #10 fro

[Bug target/115862] New: [15] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862 Bug ID: 115862 Summary: [15] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b Product: gcc Version: 15.0 Status: UNCONFIRMED Severity:

[Bug target/115741] New: [15] RISC-V: ICE in vectorizable_load, at tree-vect-stmts.cc:11524

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115741 Bug ID: 115741 Summary: [15] RISC-V: ICE in vectorizable_load, at tree-vect-stmts.cc:11524 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug tree-optimization/115387] [15 regression] RISC-V: ICE in iovsprintf.c since r15-1081-ge14afbe2d1c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug target/115387] New: [15] RISC-V: ICE in iovsprintf.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 Bug ID: 115387 Summary: [15] RISC-V: ICE in iovsprintf.c Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug tree-optimization/115220] [15 Regression] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #1) > Can you provide the preprocessed source? I attached the -freport-bug output. Please lmk if you need anything else!

[Bug tree-optimization/115220] [15 Regression] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220 --- Comment #2 from Edwin Lu --- Created attachment 58283 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58283&action=edit -freport-bug output

[Bug target/115220] New: [15] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220 Bug ID: 115220 Summary: [15] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug testsuite/115166] New: RISC-V: flakey relocation truncated to fit: R_RISCV_GPREL_I against `.LANCHOR1' in slp_run-2.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115166 Bug ID: 115166 Summary: RISC-V: flakey relocation truncated to fit: R_RISCV_GPREL_I against `.LANCHOR1' in slp_run-2.c Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/115142] [14/15 Regression] Unrecognizable insn in extract_insn, at recog.cc:2812 with -ftree-ter

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115142 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #1 from

[Bug lto/114662] [14 regression] new test case c_lto_pr113359-2 from r14-9841-g1e3312a25a7b34 fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114662 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug rtl-optimization/114515] [14 Regression] Failure to use aarch64 lane forms after PR101523

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114515 --- Comment #8 from Edwin Lu --- (In reply to Robin Dapp from comment #7) > There is some riscv fallout as well. Edwin has the details. I haven't done an in depth analysis but the full list of new riscv scan-dump failures can be found here: ht

[Bug target/114175] [13/14] Execution test failures on gcc.dg/c23-stdarg-6.c on multiple targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #32 from Edwin Lu --- riscv patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647963.html tested with rv64gcv-lp64d. waiting on precommit testing results

[Bug tree-optimization/113281] [11/12/13 Regression] Latent wrong code due to vectorization of shift reduction and missing promotions since r9-1590

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #25 fro

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #19 from Edwin Lu --- While debugging, I found that this testcase also breaks on x86_64 when optimizations are enabled (-O1 -> -O3). Godbolt: https://godbolt.org/z/ecs5MPds8 There may be other targets that fail as well. I haven't

[Bug middle-end/114197] [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 --- Comment #3 from Edwin Lu --- Patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647031.html

[Bug middle-end/114197] [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug middle-end/114197] New: [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 Bug ID: 114197 Summary: [14] middle-end: ICE in verify_dominators Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #16 from Edwin Lu --- (In reply to palmer from comment #15) > It's a little easier to see from the float version of the code. > > $ cat gcc/testsuite/gcc.dg/c23-stdarg-6.c > /* Test C23 variadic functions with no named parameters,

[Bug target/114175] [14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #4 from Edwin Lu --- (In reply to Jakub Jelinek from comment #3) > (In reply to Edwin Lu from comment #2) > > Applied the patch on top of r14-9243-g02ca9d3f0c5. Looks like the problem is > > still there. > > - else if (TYPE_NO_NAMED

[Bug target/114175] [14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #2 from Edwin Lu --- (In reply to Jakub Jelinek from comment #1) > Does the > https://gcc.gnu.org/pipermail/gcc-patches/2024-February/646882.html > patch fix that? > The test was committed ahead exactly to find out what targets have

[Bug target/114175] New: [14] RISC-V: Execution tests on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 Bug ID: 114175 Summary: [14] RISC-V: Execution tests on gcc.dg/c23-stdarg-6.c Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compo

[Bug target/114122] New: RISC-V: poor code generation in calling convention with vlen > 4096

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114122 Bug ID: 114122 Summary: RISC-V: poor code generation in calling convention with vlen > 4096 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/113913] New: [14] RISC-V: suboptimal code gen for intrinsic vcreate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913 Bug ID: 113913 Summary: [14] RISC-V: suboptimal code gen for intrinsic vcreate Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

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