https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119361
--- Comment #3 from Edwin Lu <ewlu at rivosinc dot com> --- (In reply to Robin Dapp from comment #2) > I looked into this some more and it points to a general deficiency in how we > handle the split between VLA and VLS modes. > With ...bits=zvl the RVVM1SI etc modes. become VLS modes. In turn, this > means that whenever we expand e.g. a vector(4) int we get an RVVM1SI mode > back. > But not all expanders (like vec_extract) are implemented for those modes but > just for the "real" VLS modes like V4SI. As we "convert" back and forth > between those modes and lack some expanders the resulting code is worse. > > I think a bit of an overhaul is necessary here for GCC 16. Right now I > suppose for some cases you'll get better codegen without ...bits=zvl. There > are also cases where zvl gets us better code, though :/ I'm not familiar enough with how the two modes interact with each other but I guess my question is, why do we have so many conversions between the two modes? What's the benefit of using VLA modes for VLS codegen and vice versa? It seems rather counterintuitive to me to have these two modes blend together regardless of compiling for vla or vls.
