Hi all ..
I'm currently porting GCC into a new processor, and I have a problem in
instruction scheduling ...
The case is like this:
In the machine description (*.md) file, sometimes I emit a single RTL
instruction into multiple ASM instruction. The problem is, in some case I
need to emit an oper
Sorry, no need already to bother with the last question, already knew that it
is (again) generated automatically from the Machine description file
petruk_gile wrote:
>
> Thanks .. your reply is really helpful ...
>
> Btw, I checked the MIPS backend at MIPS.c, but I ca
Thanks .. your reply is really helpful ...
Btw, I checked the MIPS backend at MIPS.c, but I can't find the definition
of some functions such as:
get_attr_hazard(), gen_hazard_nop (), etc.
Anyone know where those functions defined?
Ian Lance Taylor-3 wrote:
>
> petruk_g
Hi ALL
I'm a pure beginner in GCC, and currently working on a project to implement
instruction scheduling for a new DSP processor. This processor doesn't have
pipeline interlock, so the compiler HAVE to schedule the instruction without
relying on hardware help anymore
The problem is, I'm a