Thanks .. your reply is really helpful  ...

Btw, I checked the MIPS backend at MIPS.c, but I can't find the definition
of some functions such as: 

get_attr_hazard(), gen_hazard_nop (), etc. 

Anyone know where those functions defined? 




Ian Lance Taylor-3 wrote:
> 
> petruk_gile <[EMAIL PROTECTED]> writes:
> 
>> I'm a pure beginner in GCC, and currently working on a project to
>> implement
>> instruction scheduling for a new DSP processor. This processor doesn't
>> have
>> pipeline interlock, so the compiler HAVE to schedule the instruction
>> without
>> relying on hardware help anymore .... 
>> 
>> The problem is, I'm a very beginner in GCC. I think the scheduling in GCC
>> is
>> activated by INSN_SCHEDULING variable (in automatically generated file:
>> insn-attr.h), but I don't even know how to  activate this variable.
> 
> INSN_SCHEDULING will automatically be turned on if you have any
> define_insn_reservation clauses in your CPU.md file.  See the
> "Processor pipeline description" documentation in the gcc internals
> manual.
> 
> That said, the gcc scheduler unfortunately does not work very well for
> processors which do not have hardware interlocks.  The scheduler will
> lay out the instructions more or less optimally.  But the scheduler
> has no ability to insert nops when they are required to satisfy
> interlock constraints.
> 
> I know of two workable approachs.  You can either insert the required
> nops in the TARGET_MACHINE_DEPENDENT_REORG pass or in the
> TARGET_ASM_FUNCTION_PROLOGUE hook.  I personally prefer the latter
> approach, as it takes effect after all other instruction rearrangement
> is complete, but there are existing backends which use the former.
> 
> For an example of inserting nops in TARGET_MACHINE_DEPENDENT_REORG,
> see the MIPS backend, specifically mips_avoid_hazards.  For an example
> of inserting nops in TARGET_ASM_FUNCTION_PROLOGUE, see the FRV
> backend, specifically frv_pack_insns.
> 
> Ian
> 
> 

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