Re: Zero/Sign extension elimination using value ranges

2014-05-19 Thread Jakub Jelinek
On Tue, May 20, 2014 at 12:27:31PM +1000, Kugan wrote: > 1. Handling NOP_EXPR or CONVERT_EXPR that are in the IL because they > are required for type correctness. We have two cases here: > > A) Mode is smaller than word_mode. This is usually from where the > zero/sign extensions are showing up in

Zero/Sign extension elimination using value ranges

2014-05-19 Thread Kugan
This is based on my earlier patch https://gcc.gnu.org/ml/gcc-patches/2013-10/msg00452.html. Before I post the new set of patches, I would like to make sure that I understood review comments and my idea makes sense and acceptable. Please let me know If I am missing anything or my assumptions are wr

Re: negative latencies

2014-05-19 Thread shmeel gutl
On 19-May-14 01:02 PM, Ajit Kumar Agarwal wrote: Is it the case of code speculation where the negative latencies are used? No. It is an exposed pipeline where instructions read registers during the required cycle. So if one instruction produces its results in the third pipeline stage and a seco

dynamic_cast of a reference and -fno-exceptions

2014-05-19 Thread Daniel Gutson
Hi, should gcc warn at least if a dynamic_cast of a reference is used when -fno-exceptions is specified? At least 4.8.2 doesn't complain. If so, I can implement the fix. Example: struct Base { virtual void f(){} }; struct Der : Base {}; int main() { Der d; Base& b = d; dyna

Re: we are starting the wide int merge

2014-05-19 Thread Richard Sandiford
Richard Sandiford writes: > Gerald Pfeifer writes: >> On Sat, 17 May 2014, Richard Sandiford wrote: >>> To rule out one possibility: which GCC are you using for stage1? >> >> I think that may the smoking gun. When I use GCC 4.7 to bootstrap, >> FreeBSD 8, 9 and 10 all build fine on i386 (= i486)

[GSoC] first phase

2014-05-19 Thread Prathamesh Kulkarni
Hi, Unfortunately I shall need to take this week off, due to university exams, which are up-to 27th May. I will start working from 28th on pattern matching with decision tree, and try to cover up for the first week. I am extremely sorry about this. I thought I would be able to do both during exa

Re: [GSoC] writing test-case

2014-05-19 Thread Michael Matz
Hi, On Thu, 15 May 2014, Richard Biener wrote: > To me predicate (and capture without expression or predicate) > differs from expression in that predicate is clearly a leaf of the > expression tree while we have to recurse into expression operands. > > Now, if we want to support applying predica

Re: adding support for vxworks os variants

2014-05-19 Thread Olivier Hainque
On May 19, 2014, at 15:41 , Olivier Hainque wrote: > For vxsim or smp, having entirely separate toolchains with different triplets > for so minor differences seemed overkill and impractical for users, so we have > added "-vxsim" and "-vxsmp" command line options to our toolchains to help. > > We

adding support for vxworks os variants

2014-05-19 Thread Olivier Hainque
Hello, Here is a quick description of changes we would like to contribute to the VxWorks ports, with a preliminary query to maintainers on what would be the most appropriate form for such changes to be deemed acceptable: On a few CPU families, variants of the VxWorks OS are available. Typically

Re: Using particular register class (like floating point registers) as spill register class

2014-05-19 Thread Andrew Haley
On 05/19/2014 01:19 PM, Ramana Radhakrishnan wrote: > On Mon, May 19, 2014 at 1:02 PM, Andrew Haley wrote: >> On 05/16/2014 05:20 PM, Ian Bolton wrote: On 05/16/2014 12:05 PM, Kugan wrote: > > > On 16/05/14 20:40, pins...@gmail.com wrote: >> >> >>> On May 16, 2014, at

Re: Offload Library

2014-05-19 Thread Kirill Yukhin
Hello, Thomas! On 16 May 19:30, Thomas Schwinge wrote: > On Fri, 16 May 2014 15:47:58 +0400, Kirill Yukhin > wrote: > > To support the offloading features for Intel's Xeon Phi cards > > we need to add a foreign library (liboffload) into the gcc repository. > > As written in the README,

Re: Offload Library

2014-05-19 Thread Kirill Yukhin
Hello Ian, On 16 May 07:07, Ian Lance Taylor wrote: > On Fri, May 16, 2014 at 4:47 AM, Kirill Yukhin > wrote: > > > > To support the offloading features for Intel's Xeon Phi cards > > we need to add a foreign library (liboffload) into the gcc repository. > > README with build instructions

RE: Using particular register class (like floating point registers) as spill register class

2014-05-19 Thread Ian Bolton
> > > > Please can you try that on trunk and report back. > > OK, this is trunk, and I'm not longer seeing that happen. > > However, I am seeing: > >0x007fb76dc82c <+160>: adrpx25, 0x7fb7c8 >0x007fb76dc830 <+164>: add x25, x25, #0x480 >0x007fb76dc834 <+168>: f

Re: Using particular register class (like floating point registers) as spill register class

2014-05-19 Thread Ramana Radhakrishnan
On Mon, May 19, 2014 at 1:02 PM, Andrew Haley wrote: > On 05/16/2014 05:20 PM, Ian Bolton wrote: >>> On 05/16/2014 12:05 PM, Kugan wrote: On 16/05/14 20:40, pins...@gmail.com wrote: > > >> On May 16, 2014, at 3:23 AM, Kugan >>> wrote: >> >> I would like to know

Re: Using particular register class (like floating point registers) as spill register class

2014-05-19 Thread Andrew Haley
On 05/16/2014 05:20 PM, Ian Bolton wrote: >> On 05/16/2014 12:05 PM, Kugan wrote: >>> >>> >>> On 16/05/14 20:40, pins...@gmail.com wrote: > On May 16, 2014, at 3:23 AM, Kugan >> wrote: > > I would like to know if there is anyway we can use registers from > particular regi

RE: negative latencies

2014-05-19 Thread Ajit Kumar Agarwal
Is it the case of code speculation where the negative latencies are used? Thanks & Regards Ajit -Original Message- From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of shmeel gutl Sent: Monday, May 19, 2014 12:23 PM To: Andrew Pinski Cc: gcc@gcc.gnu.org; Vladimir Makar