Is it the case of code speculation where the negative latencies are used? Thanks & Regards Ajit -----Original Message----- From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of shmeel gutl Sent: Monday, May 19, 2014 12:23 PM To: Andrew Pinski Cc: gcc@gcc.gnu.org; Vladimir Makarov Subject: Re: negative latencies
On 19-May-14 09:39 AM, Andrew Pinski wrote: > On Sun, May 18, 2014 at 11:13 PM, shmeel gutl > <shmeelg...@shmuelhome.mine.nu> wrote: >> Are there hooks in gcc to deal with negative latencies? In other >> words, an architecture that permits an instruction to use a result >> from an instruction that will be issued later. > Do you mean bypasses? If so there is a bypass feature which you can use: > https://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.h > tml#index-data-bypass-3773 > > Thanks, > Andrew Pinski Unfortunately, bypasses in the pipeline description is not enough. They only allow you to calculate the latency of true dependencies. They are also forced to be zero or greater. The real question is how the scheduler and register allocator can deal with negative latencies. Thanks Shmeel >> At first glance it seems that it will will break a few things. >> 1) The definition of dependencies cannot come from the simple >> ordering of rtl. >> 2) The scheduling problem starts to look like "get off the train 3 >> stops before me". >> 3) The definition of live ranges needs to use actual instruction >> timing information, not just instruction sequencing. >> >> The hooks in the scheduler seem to be enough to stop damage but not >> enough to take advantage of this "feature". >> >> Thanks >> > > ----- > No virus found in this message. > Checked by AVG - www.avg.com > Version: 2014.0.4577 / Virus Database: 3950/7515 - Release Date: > 05/18/14
