On Mon, 5 Jan 2009, Sterling Augustine wrote:
> Could I ping on the issue described below?
>
> Bob can no longer maintain the Xtensa port for GCC, and I don't think he
> is even reading the GCC mailing list any more. For the forseeable
> future, I am responsible for the Xtensa port of GCC here at
Peter O'Gorman wrote:
>
> The problems start with r109149 - this patch:
> http://gcc.gnu.org/ml/gcc-patches/2005-12/msg01905.html
>
> With this patch reverted we can build qt on Tru64 with gcc-4.2.4.
>
> I have not yet built trunk on this platform, when I tired bootstrap
> failed, will try agai
Maxim and Vladimir Wrote:
>>> Anyone can help me through this please?
>>>
>> It was supposed to have two latency definitions at most (one in
>> define_insn_reservation and another one in define_bypass). That time it
>> seemed enough for all processors supported by GCC. It also simplified
>>
Vladimir Makarov wrote:
Ye, Joey wrote:
...
Anyone can help me through this please?
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplif
Ye, Joey wrote:
When I write schedule model for following instructions:
Insn1: mov %r1, %r2
Insn2: mov %r1, %r3
Insn3: foo %r2, %r3 (foo is a 3 op insn, for example, %r3 = %r3 << %r2)
Latency from insn1 to insn3 is x cycles, and latency from insn2 to insn3 is y
cycles. x != y.
Both insn1 and
On Mon, Jan 05, 2009 at 11:39:55AM -0800, Chris wrote:
> Is it possible to have some sort of protocol in gcc, so that any
> unimplemented library function uses #warning or static_assert(0,"regex
> not implemented") to not to confuse any future users? I don't think
> gcc should provide headers tha
Could I ping on the issue described below?
Bob can no longer maintain the Xtensa port for GCC, and I don't think he
is even reading the GCC mailing list any more. For the forseeable
future, I am responsible for the Xtensa port of GCC here at Tensilica.
What should I do to move the process for
Hi,
I know that regex in c++0x was not implemented, but later I tried it
anyway and my code compiled but did not do a match. I looked at the
tr1_impl and the most functions have a \TODO implement and the function
just returns a default "do nothing".
Is it possible to have some sort of pro
On Tue, Jan 06, 2009 at 01:12:08AM +0800, Jie Zhang wrote:
> >[...] Other alternatives would include having
> >emutls define something in addition to HAVE_TLS that activates the
> >!HAVE_TLS implementation in libmudflap/mf-hooks3.c.
>
> Thanks for your help! How about the attached patch, which fo
Hi Frank,
Frank Ch. Eigler wrote:
Jie Zhang writes:
To break the recursive loop, one solution is to force emutls to call
the real calloc. [...]
If it were acceptable to change emutls on account of mudflap, this
sort of thing could work. Other alternatives would include having
emutls define
daniel tian wrote:
Hi Dr. Uday Khedker:
Happy New Year!
I met hazard problem. And I have debuged this error for a few
days. I wrote DFA to avoid load hazard, but still it exists. I wonder
whether in default the command './cc1 hazard.c' doesn't compile the
file with DFA. And in default wit
Bingfeng Mei wrote:
I found if I define a new register class that covers both GR_REGS and PR_REGS, the issue can be solved. New IRA spill the predicate register to general regsister first instead of memory. Is this right approach?
#define IRA_COVER_CLASSES \
{ \
GRP
Bingfeng Mei wrote:
Hello,
I recently ported our GCC to new IRA by following mainline development. The
only interface I added is IRA_COVER_CLASSES. Our architecture has predicate
register file. When predicate register has to be spilled, the new IRA produces
inferior code to the old register a
When I write schedule model for following instructions:
Insn1: mov %r1, %r2
Insn2: mov %r1, %r3
Insn3: foo %r2, %r3 (foo is a 3 op insn, for example, %r3 = %r3 << %r2)
Latency from insn1 to insn3 is x cycles, and latency from insn2 to insn3 is y
cycles. x != y.
Both insn1 and insn2 are insn_res
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