Ye, Joey wrote:
When I write schedule model for following instructions:
Insn1: mov %r1, %r2
Insn2: mov %r1, %r3
Insn3: foo %r2, %r3 (foo is a 3 op insn, for example, %r3 = %r3 << %r2)
Latency from insn1 to insn3 is x cycles, and latency from insn2 to insn3 is y
cycles. x != y.
Both insn1 and insn2 are insn_reservation_mov. Insn3 are insn_reservation_foo.
When I define bypass for them I found I couldn't do it. I can only define one
bypass from mov to foo, like this:
(define_bypass x "insn_reservation_mov" "insn_reservation_foo" "condition1")
If I define following bypass too, gcc will report error:
(define_bypass y "insn_reservation_mov" "insn_reservation_foo" "condition2")
genautomata: bypass `insn_reservation_lea - insn_reservation_foo' is already
defined
Anyone can help me through this please?
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplified
semantics definition when two bypass conditions returns true for the
same insn pair.
If you really need more one bypass for insn pair, I could implement
this. Please, let me know. In this case semantics of choosing latency
time could be
o time in first bypass occurred in pipeline description whose condition
returns true
o time given in define_insn_reservation
