From: Pavel Pisa
Signed-off-by: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/console/tms570-sci.c | 38 ++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c
b/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c
From: Pavel Pisa
These enhancements are laying already for long term in TMS570
development branch for RTEMS 4.11 and they should be
available for mainline as well.
https://github.com/AoLaD/rtems/tree/tms570-bsp-with-hwinit
The main purpose of these changes is attempt to archive small but
From: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/preinstall.am | 8
1 file changed, 8 insertions(+)
diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am
b/c/src/lib/libbsp/arm/tms570/preinstall.am
index 2fddba8..be8e42e 100644
--- a/c/src/lib/libbsp/arm/tms570/preinstall.am
+++ b/c
From: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/include/tms570-pins.h | 10 +
.../arm/tms570/include/tms570ls3137zwt-pins.h | 690 +
2 files changed, 700 insertions(+)
create mode 100644 c/src/lib/libbsp/arm/tms570/include/tms570-pins.h
create mode 100644 c/src/lib
From: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/Makefile.am| 3 +
.../lib/libbsp/arm/tms570/include/tms570-pinmux.h | 136 +++--
c/src/lib/libbsp/arm/tms570/include/tms570.h | 3 +
c/src/lib/libbsp/arm/tms570/pinmux/pinmux.c| 123
From: Pavel Pisa
---
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4
1 file changed, 4 insertions(+)
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 35c8002..e83b55c 100644
--- a/c/src/lib/libbsp/arm/shared/arm
From: Pavel Pisa
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar
From: Pavel Pisa
These changes allows to boot Raspberry Pi 2 with recent firmware
which start system in ARM hypervisor (HYP) mode.
There are more changes to correct/make compile cache manager
functions for more boards (till now only Zynq, Altera Cyclone
and LPC32xx have non empty implementation
From: Pavel Pisa
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
---
cpukit/score/cpu/arm/rtems/score/arm.h | 4
cpukit/score/cpu/arm/rtems/score/cpu.h | 7 +--
2 files changed, 9 insertions(+), 2 deletions
From: Pavel Pisa
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used
From: Pavel Pisa
This support is required when newer firmware is used on
Raspberry Pi 2 boards.
---
c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 3 +++
c/src/lib/libbsp/arm/raspberrypi/configure.ac | 4
2 files changed, 7 insertions(+)
diff --git a/c/src/lib/libbsp/arm/raspberrypi
From: Pavel Pisa
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
---
c/src/lib/libcpu/arm
From: Pavel Pisa
The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2,
clean by individual lines works on RPi1 and RPi2.
---
c/src/lib/libbsp/arm/raspberrypi/misc/vc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/c/src/lib/libbsp/arm
From: Pavel Pisa
Synchronize each cluster of sections of the same type separately
to support even cases where text and data are allocated from different
areas (for example due allocation from different MPU protection regions).
rtems_cache_instruction_sync_after_code_change is called even to
From: Pavel Pisa
The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be
From: Pavel Pisa
When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET
From: Pavel Pisa
The changes correct libdl operation on targets which do not snoop
data change during instruction cache fill.
Text section/the first 1 MB of data has been noncacheable
after VideoCore support inclusion. Enabling cache of this
area has revealed problem with stalled data left by
From: Pavel Pisa
This fix strange behavior where some stale content has been
stored in level 2 cache before RTEMS has been start from U-boot
which has reappeared after MMU enable and shadow vector
table at start of SDRAM.
---
c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c | 14
From: Pavel Pisa
Memory content changes caused by relocation has to be
propagated to memory/cache level which is used/snooped
during instruction cache fill.
---
cpukit/libdl/rtl-elf.c | 3 +++
cpukit/libdl/rtl-obj.c | 67 --
cpukit/libdl/rtl
From: Pavel Pisa
Signed-off-by: Pavel Pisa
---
c/src/lib/libbsp/arm/raspberrypi/misc/vc.c | 35 ++
1 file changed, 2 insertions(+), 33 deletions(-)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
b/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
index 0bec0c2
From: Pavel Pisa
Enable even the first megabyte of SDRAM to be cache-able after
problems with stale cache content has been resolved by previous commit.
Because major part of application usually fits to the first
megabyte this speedups test dhrystone application by factor 40.
---
.../arm
From: Pavel Pisa
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are
From: Pavel Pisa
Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it
From: Pavel Pisa
The series implements Raspberry Pi 2 (BCM2836) SMP support.
The first two patches modify ARM Cortex-A common CP15 support
to expose clean by level cache operations to the BSP code.
Clean and invalidation of L1 cache is required when the secondary
CPU is booted. But the
From: Pavel Pisa
The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
---
c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 39 --
1 file changed, 30 insertions(+), 9
From: Rohini Kulkarni
---
.../libbsp/arm/raspberrypi/include/raspberrypi.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
b/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
index 911b86b..4cedc4c 100644
From: Pavel Pisa
---
c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 2 --
c/src/lib/libbsp/arm/raspberrypi/configure.ac | 5 +++--
c/src/lib/libbsp/arm/raspberrypi/startup/{linkcmds => linkcmds.in} | 0
3 files changed, 3 insertions(+), 4 deleti
From: Pavel Pisa
---
c/src/lib/libbsp/arm/raspberrypi/include/irq.h | 5 +
c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h | 18 +++---
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/irq.h
b/c/src/lib
From: Pavel Pisa
---
c/src/lib/libbsp/arm/raspberrypi/configure.ac| 14 ++
c/src/lib/libbsp/arm/raspberrypi/startup/linkcmds.in | 2 ++
2 files changed, 16 insertions(+)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/configure.ac
b/c/src/lib/libbsp/arm/raspberrypi
From: Pavel Pisa
Protection by rtems_interrupt_disable() is incompatible with SMP build.
Actual page table entries manipulation function does not need locking
and disabling cache and can be run concurrently even on multiple
CPUs as long as changes do not modify same region. If the function
is
From: Pavel Pisa
---
.../libbsp/arm/raspberrypi/include/raspberrypi.h | 142 -
1 file changed, 140 insertions(+), 2 deletions(-)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
b/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
index 4cedc4c
From: Pavel Pisa
New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level
can be used to maintain single cache level (instruction or data).
---
c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 108 ++---
1 file changed, 60 insertions(+), 48 deletions
From: Pavel Pisa
It has advantage that it is designed as free-running counter
with compare registers and can easily serve for for both
timecounter and tick interrupt.
---
c/src/lib/libbsp/arm/raspberrypi/clock/clockdrv.c | 98 ++-
1 file changed, 62 insertions(+), 36
From: Pavel Pisa
---
c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 3 +
c/src/lib/libbsp/arm/raspberrypi/include/bsp.h | 3 +
c/src/lib/libbsp/arm/raspberrypi/irq/irq.c | 18 +++
c/src/lib/libbsp/arm/raspberrypi/startup/bspsmp.c | 122 +
.../libbsp
From: Pavel Pisa
The code introduces initialization algorithms bases on Ti HalCoGen
generated files. The most of the code has been rewritten to use
RTEMS much more complete header files. This allowed to replace most
of the hardcoded hexadecimal values by appropriate fields macros documenting
how
From: Pavel Pisa
Generated header file ti_herc/reg_spi.h contains complete registers
and fields set for Ti MibSPI peripheral.
Care has to be taken that only TMS570_SPI1, TMS570_SPI3 and TMS570_SPI5
are of this complete multibuffer type. TMS570_SPI2 and TMS570_SPI4
have substantial part of
From: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/README | 104 +
1 file changed, 82 insertions(+), 22 deletions(-)
diff --git a/c/src/lib/libbsp/arm/tms570/README
b/c/src/lib/libbsp/arm/tms570/README
index f48744f..840ce68 100644
--- a/c/src/lib/libbsp/arm
From: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/Makefile.am | 21 +
c/src/lib/libbsp/arm/tms570/configure.ac | 4
2 files changed, 25 insertions(+)
diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am
b/c/src/lib/libbsp/arm/tms570/Makefile.am
index c4d39bc..012ce23
From: Pavel Pisa
The configuration is specific for TMS570LS3137 based HDK.
But pins configuration can be easily changed in
rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c
file.
---
.../arm/tms570/hwinit/bspstarthooks-hwinit.c | 393 ++
.../libbsp/arm/tms570/hwinit
From: Pavel Pisa
---
c/src/lib/libbsp/arm/tms570/preinstall.am | 13 +
1 file changed, 13 insertions(+)
diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am
b/c/src/lib/libbsp/arm/tms570/preinstall.am
index be8e42e..7d79184 100644
--- a/c/src/lib/libbsp/arm/tms570/preinstall.am
From: Pavel Pisa
When GCC option -march is not specifies i386-rtems toolchain
defaults to i386 architecture instruction set. It does not
provide atomic instructions which results in really inefficient
atomic_fetch_or even on UP build.
SMP build is broken with i386 set because libatomic and GCC
From: Pavel Pisa
The elimination of global interrupt lock is necessity condition
but far from being sufficient for RTEMS x86 SMP support.
Provided changes allows to build i386 BSP with configure
option --enable-smp. The build BSP runs in UP and SMP
configurations on QEMU when only one/boot CPU
From: Pavel Pisa
---
c/src/lib/libbsp/i386/pc386/clock/ckinit.c | 19 ++---
c/src/lib/libbsp/i386/pc386/console/inch.c | 10 +++--
c/src/lib/libbsp/i386/pc386/console/keyboard.c | 55 --
c/src/lib/libbsp/i386/pc386/console/vt.c | 13 +++---
c/src/lib
From: Pavel Pisa
The single write to memory or ioport output are mostly
atomic operations already. The proper memory synchronization barrier
should be used around them to guarantee ordering (sync or eieio
on PowerPC for example) but because I have not found settable
portable primitive only
Hello Martin,
this is the right and planned change.
What are your results of testing the BSP?
Are there some stability issues or your combination
with HALcogen code and FPU passes tests suites.
Best wishes,
Pavel
On Thursday 26 of March 2015 21:21:26 Martin Galvan wrote:
> ---
>
Hello all,
I would like to inform you that Premysl Houdek is near to finishing
preparation of complete registers header files for TMS570LS3137.
The register and fields definition are interactively retrieved
with help of some macro from MCU PDF manual files.
We decided to store retrieved data in JS
Hello Martin,
On Wednesday 01 of April 2015 21:08:19 Martin Galvan wrote:
> On Wed, Apr 1, 2015 at 8:01 AM, Pavel Pisa wrote:
> > To Martin Galvan: What is your opinion? Would you join the work in
> > this direction?
>
> So if I understood correctly, what you did was conve
Hello Gedare,
On Wednesday 01 of April 2015 16:38:05 Gedare Bloom wrote:
> On Wed, Apr 1, 2015 at 7:01 AM, Pavel Pisa wrote:
> > https://github.com/AoLaD/rtems-tms570-utils/blob/Headers/headers/headers/
> >CRC.h
>
> For headers/code that is automatically generated, I&#
Hello Hugo,
On Wednesday 01 of April 2015 12:58:33 zj...@york.ac.uk wrote:
> Hi:
>
> I am a student to work with RTEMS these days.
>
> I like this OS, but I found there's few information about RTEMS, I am
> really desired to know how can I add a new driver for it, such as LCD
> driver or others.
>
Hello Yang Qiao,
On Tuesday 07 of April 2015 00:00:33 QIAO YANG wrote:
> I've implemented a simple framebuffer, but I've got no idea how to test it.
>
> I've got Alan's rki and I made a sample to test the mailbox, the
> framebuffer information seems to be successfully set and get (width,
> height,
Hello QIAO YANG,
I have found that I have not succeed to find time to reply to this one.
I have not any more founded resolution to these.
On Tuesday 07 of April 2015 22:55:07 QIAO YANG wrote:
> On Apr 07, 2015, at 06:50 AM, Pavel Pisa wrote:
> > ARMV7_MMU_DATA_READ_WRITE
> >
&
Hello Martin,
On Monday 06 of April 2015 20:18:46 Martin Galvan wrote:
> On Wed, Apr 1, 2015 at 7:35 PM, Pavel Pisa wrote:
> > Hello Martin,
>
> Hi, sorry for the late answer.
No problem, I am in overload mode too.
> > the solution is to define simple JSON format which
Hello YANG Qiao,
On Tuesday 05 of May 2015 01:08:11 QIAO YANG wrote:
> Since I haven't yet received any respond of my last mail and I've now got
> the names of mentors who would instruct me, I create a new thread for a
> simple resume and post my questions .
>
> First of all, I've managed to use m
+ * @retval -1 no suitable mode found
> >> + * @retval -2 bad format of the video_string
> >> + * @retval -3 automatic mode selection requested
> >> + * @retval -4 request to not initialize graphics
> >> + * @retval -5 no mode requested/empty video string
> >>*/
> >> -static uint16_t find_mode_using_cmdline(Mode_params *mode_list,
> >> -uint8_t list_length)
> >> +static uint16_t find_mode_from_string(Mode_params *mode_list,
> >> + uint8_t list_length,
> >> + const char *video_string)
> >
> > Is it ok to cast a negative enum value into a uint16_t?>
>
> I don't quite understand, what do you mean by ok.
> I use negative numbers to get values from the end of uint16_t range
> which should not overlap with possible valid mode numbers. Return value
> is used to inform the user why the driver was not initialized. The deciding
> switch cases (below) then have explicit casts into a uint16_t, so it
> is compared correctly.
This works for most/all C implementations but if I remember it is
defined as implementation specific behavior and does not conform
requirements for portable and code. But I think that above suggestion
should help to eliminate all these cases in the code.
Best wishes,
Pavel Pisa
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Hello Joel,
On Saturday 23 of May 2015 16:44:09 Joel Sherrill wrote:
> Hi
>
> A LOT has happened since our last release. The release
> page (https://devel.rtems.org/wiki/Release/4.11) has a
> lot of the changes listed but a quick scan shows that
> at least:
>
> + SMP not mentioned
> + dynamic load
Hello all,
Premysl Houdek has prepared new and hopefully near ready
complete header files for TMS570LS3137 microcontroller.
They are based on PDF documentation and license is
RTEMS compatible. The scripts used during process can be
found in
https://github.com/AoLaD/rtems-tms570-utils/tree/heade
Hello Yang Qiao,
On Tuesday 02 of June 2015 22:58:09 QIAO YANG wrote:
> For the graphic text output, I've implemented two functions _RPI_initvideo
> and _RPI_outch, used to print chars to graphic. They are declared in bsp.h
> and implemented in outch.c as we've done in i386 bsp.
>
> 1. The _RPI_i
Hello Gedare,
thanks for response.
On Friday 05 of June 2015 18:18:15 Gedare Bloom wrote:
> On Tue, Jun 2, 2015 at 9:39 AM, Pavel Pisa wrote:
> > Please, look on the files and express your opinion.
> > The new temporary top level header files is tms5702.h.
> > It should re
des these
> Should I make it same? not checked TCR PLL FLEX EMAC CCMSR
> - i dont see library counterparts
On Friday 05 of June 2015 21:39:30 Gedare Bloom wrote:
> On Fri, Jun 5, 2015 at 3:01 PM, Pavel Pisa wrote:
>
> Certainly! I don't mind that the author notice and license appea
Hello Sebastian and others,
On Friday 12 of June 2015 17:47:42 Sebastian Huber wrote:
> - Gedare Bloom schrieb:
> > I see. It provides the mutual exclusion for (SMP) applications that
> > rely on interrupt_disable/enable locks?
> >
> > I guess we can never get rid of it as long as we allow fo
for graphic output is is not so critical and for real embedded
systems small keyboard on SPI can be usable as well.
SPI on RPi is not/should not be a problem. I can provide examples
of SPI based keyboard support for RTEMS and even HW implementation
used on ou
Hello everybody,
I would like to inform that full text of the bachelor
thesis
Drivers and Libraries Enabling RTEMS OS GUI on Current PC Graphics Cards
has been defended and is available online
https://dspace.cvut.cz/handle/10467/61467
https://dspace.cvut.cz/bitstream/handle/10467/61467/F3-BP-2
Hello Qiao Yang,
I have prepared testing on RPi B+ hardware last days
I have got to test your RTEMS branch
https://github.com/yangqiao/rtems
I have tried
e89884b add memory table entry for frame buffer (try to cover all
possibility, may be larger afterward if it's not enough)
and then
Hello Qiao Yang,
thanks for status report.
On Wednesday 01 of July 2015 23:53:51 QIAO YANG wrote:
> On Jun 30, 2015, at 12:41 PM, Pavel Pisa wrote:
>
> Both should work, I've tested before push. BTW, because I've found the way
> I refactor outch is not as clean as I imagi
Hello Qiao Yang,
On Thursday 02 of July 2015 01:23:24 桥 杨 wrote:
> >
> > The final - RTEMS-4.11 intended option for i386 is named video
> >
> > --video=auto|off|1024x768-32
> >
> > console selection is controlled by option
> >
> > --console=com1
>
> I tried to retrieve ATAG cmdline by mailbox p
jects. If there is no
objection or opinion for other solution, I prepare and check
patch with stat().
>From 4ce027b21cfde5bc6143d51d244345e05dd85cd4 Mon Sep 17 00:00:00 2001
Message-Id:
<4ce027b21cfde5bc6143d51d244345e05dd85cd4.1436800331.git.pp...@pikron.com>
From: Pavel Pisa
Date: Mon,
quot;no-builtin")));
Check for syntax to be sure, may it be I have omitted
some comma or paretheses.
Best wishes,
Pavel
--
Pavel Pisa
e-mail: p...@cmp.felk.cvut.cz
www:http://cmp.felk.cvut.cz/~pisa
university: http://dce.fel.cvut.cz/
Hello Martin and others,
On Wednesday 15 of July 2015 15:37:28 Martin Galvan wrote:
> Hello Premysl! Thanks for this patch.
>
> Could you tell us why is this patch needed, and where does the new
> formula come from? From what I saw, HALCoGen generates a macro called
> RTI_FREQ which has the value
Hello Martin,
On Wednesday 15 of July 2015 16:58:02 Martin Galvan wrote:
> On Wed, Jul 15, 2015 at 11:41 AM, Pavel Pisa wrote:
> > the code has been tested for internal RAM now.
> > We have more cleanups in the mind but headers are critical
> > for now. Premek is work
Hello Martin and others,
new proposal for TMS570 headers update can be found
in branch "tms570-bsp-new-headers" of Premysl Houdek's
RTEMS development repository
https://github.com/AoLaD/rtems
https://github.com/AoLaD/rtems/tree/tms570-bsp-new-headers/c/src/lib/libbsp/arm/tms570/include
The
Hello Martin,
On Wednesday 15 of July 2015 19:30:55 Martin Galvan wrote:
> On Wed, Jul 15, 2015 at 12:22 PM, Pavel Pisa wrote:
> > Patch provides way to the previous working state at least.
> > I would suggest to apply this patch because current mainline is broken
> > in act
Hello Joel,
On Wednesday 15 of July 2015 20:05:12 Joel Sherrill wrote:
> On 7/15/2015 12:30 PM, Martin Galvan wrote:
> > On Wed, Jul 15, 2015 at 12:22 PM, Pavel Pisa
wrote:
> >> Patch provides way to the previous working state at least.
> >> I would suggest to apply
Hello Joel,
I have been with Premek when he tested these on the target.
[PATCH 1/2] bsp/tms570: skipped 32bit field definitions and corrected single
bit fields
This one clean header files. There has been unnecessary defines
of whole registers as fields and mistake in single bit definitions
Hello Chris and Qiao Yang,
On Monday 20 of July 2015 01:12:33 Chris Johns wrote:
> On 20/07/2015 6:55 am, QIAO YANG wrote:
> > I've ported the graphic libraries into rsb so that we can build them
> > much easier. All Build passed, tested on arm with raspberrypi and i386
> > with pc386.
>
> Fantast
Hello Qiao Yang,
I have spent more time with attempt to test
your RPi code but I am not sucesfull.
I have tried direct boot to application binary
as well as U-boot based start.
I expect that problem source can be version
of my primary bootloader
bootcode.bin + start_cd.elf + start_x.elf
or co
Hello everybody,
I have decided to prepare debugging environment
during my attempts to test graphic Qiao Yang's
framebuffer support for RPi and I expect that infomation
can be interesting for more developers.
The first, I do not like to copy RTEMS image each time
to SD card for test on real hardw
Hello Qiao Yang and other,
On Monday 20 of July 2015 15:06:23 Pavel Pisa wrote:
> Hello Qiao Yang,
>
> I have spent more time with attempt to test
> your RPi code but I am not sucesfull.
> I have tried direct boot to application binary
> as well as U-boot based start.
>
&g
Hello Qiao Yang,
On Monday 20 of July 2015 20:50:32 QIAO YANG wrote:
> So it has got the right pointer for frame buffer.
>
> Please set the macros
>
> BCM2835_FBMEM_BASE to 0x1C006000
> and BCM2835_FBMEM_SIZE to 0x50
> according to your log.
I have got to testing at home where I have other RP
Hello Qiao Yang
On Tuesday 21 of July 2015 14:21:07 QIAO YANG wrote:
> Hi Pavel Pisa,
>
> On Jul 19, 2015, at 10:35 PM, Pavel Pisa wrote:
> > Hello Chris and Qiao Yang,
> >
> > On Monday 20 of July 2015 01:12:33 Chris Johns wrote:
> >> On 20/07/2015 6:55 am,
Hello Qiao Yang,
On Wednesday 22 of July 2015 11:19:35 QIAO YANG wrote:
> Hi,
>
> When I updated to the latest firmware start.elf , the graphic doesn’t show
> anymore. I haven’t yet found out what has been changed in the latest
> firmware. I’ve uploaded my firmware. I’ve retested my latest commit,
Hello Sebastian,
the first big thanks for RTEMS architectural updates.
On Thursday 23 of July 2015 11:16:03 Sebastian Huber wrote:
> The Classic RTEMS and POSIX APIs have at least three weaknesses.
>
> * Dynamic memory (the workspace) is used to allocate object pools. This
>requires a complex
Hello Sebastian,
On Thursday 23 of July 2015 13:31:23 Sebastian Huber wrote:
> Hello Pavel,
>
> thanks for your comments.
>
> On 23/07/15 12:40, Pavel Pisa wrote:
> > Hello Sebastian,
...
> > I fully understand your motivation and for small footprint system
> >
Hello Qiao Yang,
On Friday 24 of July 2015 18:04:47 QIAO YANG wrote:
> Some updates for you. I've found out that my previous problem with cmdline
> due to my minicom didn't wrap up the lines I've chosen the interface of
> vc to retrieve cmdline so that we don't need to parse the atag nor
> dev
Hello Rohini and Gedare,
On Friday 24 of July 2015 15:33:03 Gedare Bloom wrote:
> What are the values of bsp_section_bss_begin, and bsp_section_bss_size?
>
> Apparently, the memset is trying to write into the .text (code)
> section, which is a very bad thing to do indeed.
>
Qiao Yang in RPi 1 BSP
Hello Qiao Yang,
On Saturday 25 of July 2015 14:53:35 QIAO YANG wrote:
> Hi Pavel Pisa,
>
> I've added the auto-configuration for fb section in mmu table.
> I reserve a section at the end of mmu table, make the table non-const to
> avoid errors, allocate fb before mmu initia
Hello Sebastian,
On Wednesday 29 of July 2015 09:06:47 Sebastian Huber wrote:
> On 28/07/15 02:31, Pavel Pisa wrote:
> >> >I think it's much closer to what we expected. you may checkout my
> >> > github and my dropbox.
> >> >https://github.com
Hello Qiao Yang,
On Tuesday 28 of July 2015 01:35:45 Pavel Pisa wrote:
> Hello Qiao Yang,
>
> On Friday 24 of July 2015 18:04:47 QIAO YANG wrote:
> > Some updates for you. I've found out that my previous problem with
> > cmdline due to my minicom didn't wrap u
Hello Qiao Yang,
On Monday 03 of August 2015 22:06:31 QIAO YANG wrote:
> On Aug 03, 2015, at 08:34 AM, QIAO YANG wrote:
> > On Jul 29, 2015, at 02:03 PM, Chris Johns wrote:
> >> On 29/07/2015 8:04 pm, Sebastian Huber wrote:
> >>> A custom workspace initialization can be done via
> >>> bsp_work_a
Hello Qiao Ynag,
I am in a hurry now.
On Friday 07 of August 2015 00:52:43 QIAO YANG wrote:
> > You have the MMU part right. You know where VC memory starts.
> > You round it down to 1MB range (because that is step size which
> > ARM MMU provides in the actual RTEMS setup). Then you need to
> > l
Hello Chris and Rohini,
I have returned and catching the emails flow.
But please, consider that for some architectures it is critical
to have MMU table runtime alterable.
I.e. on RPi the actual memory division to cacheable
and peripheral area is know only at runtime. It depends
on user provided
Hello Giao, Joel and Gedare,
there are more technical problems to discuss.
But I start with question if RPi video support
should be unconditional. I am not sure if VideoCore
activation has some consequences to ARM system throughput
but at least it slows down startup.
So there can be resons to dis
Hello Gedare,
On Friday 21 of August 2015 16:46:41 Gedare Bloom wrote:
> I believe CANFestival comes from Pavel Pisa's group. He is active with
> RTEMS and interested in pushing forward CAN improvements, but time is
> always a problem. He's on vacation but may get to this thread after he
> gets ba
---
cpukit/libmisc/untar/untar.c | 8
1 file changed, 8 insertions(+)
diff --git a/cpukit/libmisc/untar/untar.c b/cpukit/libmisc/untar/untar.c
index aed8fed..4591a8b 100644
--- a/cpukit/libmisc/untar/untar.c
+++ b/cpukit/libmisc/untar/untar.c
@@ -28,6 +28,7 @@
#include
#include
#inc
ps://devel.rtems.org/wiki/Developer/Simulators/QEMU/CANEmulation
Relevant commits
commit 2d873a9ed3bcb8301a247f36b77227b1cd9211c0
Author: Pavel Pisa
Date: Mon Sep 7 15:24:56 2015 +0200
CAN bus simple SJA1000 PCI card emulation for QEMU
The work is based on Jin Yang GSoC 2013 work fund
Sep 7, 2015 at 5:23 AM, Pavel Pisa wrote:
> > ---
> > cpukit/libmisc/untar/untar.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/cpukit/libmisc/untar/untar.c b/cpukit/libmisc/untar/untar.c
> > index aed8fed..4591a8b 100644
> &g
The problem exists for both RTEMS untar implementations and their
variants: Untar_FromMemory(), Untar_FromFile() and rtems_tarfs_load().
---
cpukit/libfs/src/imfs/imfs_load_tar.c | 12 +++-
cpukit/libmisc/untar/untar.c | 18 +-
2 files changed, 28 insertions(+), 2
Hello Sebastian,
On Thursday 10 of September 2015 08:52:37 Sebastian Huber wrote:
> On 28/07/15 09:48, Chris Johns wrote:
> > Either scheme fits pretty well with RTEMS release cycle I think.
> > Even if we can get down to one release per year, the numbers
> > won't grow t
Hello Gedare and others,
On Thursday 10 of September 2015 05:00:27 Gedare Bloom wrote:
> Looks good. This should go on 4.11 and master? Someone can commit.
please commit to both.
> On Wed, Sep 9, 2015 at 6:09 PM, Pavel Pisa wrote:
> > The problem exists for both RTEMS untar impleme
Hello Sudarshan,
On Friday 25 of September 2015 19:13:53 sudarshan.rajagopalan wrote:
> On 2015-09-25 12:21, Daniel Gutson wrote:
> > El 25/9/2015 13:17, "sudarshan.rajagopalan"
> >
> > escribió:
> > > On 2015-09-25 11:06, Daniel Gutson wrote:
> > >> On Thu, Sep 24, 2015 at 4:49 PM, sudarshan.r
Hello Chris and others,
I have no problem if most of RTEMS makefiles are replaced by something
better but I would really regret if
/opt/rtems4.11/arm-rtemsX.YY/BSP_Z/Makefile.inc
file is not generated and installed during BSP build process.
This file holds enough information to build complex
1 - 100 of 389 matches
Mail list logo
