From: Pavel Pisa <p...@cmp.felk.cvut.cz>
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
---
c/src/lib/libbsp/arm/beagle/Makefile.am | 5 +-
c/src/lib/libbsp/arm/csb336/Makefile.am | 6 +-
c/src/lib/libbsp/arm/csb337/Makefile.am | 6 +-
c/src/lib/libbsp/arm/lpc32xx/Makefile.am | 6 +-
c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 8 +-
c/src/lib/libbsp/arm/raspberrypi/preinstall.am | 4 -
c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 5 +-
.../arm/shared/armv467ar-basic-cache/cache_.h | 134 +++++++++++++++++++++
c/src/lib/libbsp/arm/smdk2410/Makefile.am | 6 +-
c/src/lib/libcpu/arm/shared/include/cache_.h | 134 +++++----------------
10 files changed, 190 insertions(+), 124 deletions(-)
create mode 100644 c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am
b/c/src/lib/libbsp/arm/beagle/Makefile.am
index 20d3092..904cb84 100644
--- a/c/src/lib/libbsp/arm/beagle/Makefile.am
+++ b/c/src/lib/libbsp/arm/beagle/Makefile.am
@@ -126,8 +126,9 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
###############################################################################
# Special Rules #
diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am
b/c/src/lib/libbsp/arm/csb336/Makefile.am
index e2687b8..27d159f 100644
--- a/c/src/lib/libbsp/arm/csb336/Makefile.am
+++ b/c/src/lib/libbsp/arm/csb336/Makefile.am
@@ -10,6 +10,7 @@ include_HEADERS = include/bsp.h
include_HEADERS += ../../shared/include/tm27.h
include_bsp_HEADERS =
+libbsp_a_CPPFLAGS =
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -51,8 +52,9 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
diff --git a/c/src/lib/libbsp/arm/csb337/Makefile.am
b/c/src/lib/libbsp/arm/csb337/Makefile.am
index 598a67f..018bf67 100644
--- a/c/src/lib/libbsp/arm/csb337/Makefile.am
+++ b/c/src/lib/libbsp/arm/csb337/Makefile.am
@@ -13,6 +13,7 @@ include_HEADERS += include/sed1356.h
endif
include_bsp_HEADERS =
+libbsp_a_CPPFLAGS =
if ENABLE_UMON
include_umondir = $(includedir)/umon
@@ -88,8 +89,9 @@ endif
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am
b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am
index 5426323..e87c6a0 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am
+++ b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am
@@ -142,8 +142,10 @@ libbsp_a_SOURCES += misc/idle-thread.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
+
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c
diff --git a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am
b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am
index c9208d4..4b111ad 100644
--- a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am
+++ b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am
@@ -55,8 +55,7 @@ include_bsp_HEADERS += include/vc.h
include_bsp_HEADERS += include/rpi-fb.h
include_bsp_HEADERS += console/fbcons.h
-include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache_.h \
- ../../../libcpu/arm/shared/include/arm-cp15.h
+include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
###############################################################################
# Data #
@@ -153,8 +152,9 @@ libbsp_a_SOURCES += spi/spi.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c
diff --git a/c/src/lib/libbsp/arm/raspberrypi/preinstall.am
b/c/src/lib/libbsp/arm/raspberrypi/preinstall.am
index e6f0ca0..194ab79 100644
--- a/c/src/lib/libbsp/arm/raspberrypi/preinstall.am
+++ b/c/src/lib/libbsp/arm/raspberrypi/preinstall.am
@@ -162,10 +162,6 @@ $(PROJECT_INCLUDE)/bsp/fbcons.h: console/fbcons.h
$(PROJECT_INCLUDE)/bsp/$(dirst
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/fbcons.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/fbcons.h
-$(PROJECT_INCLUDE)/libcpu/cache_.h:
../../../libcpu/arm/shared/include/cache_.h
$(PROJECT_INCLUDE)/libcpu/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h
-
$(PROJECT_INCLUDE)/libcpu/arm-cp15.h:
../../../libcpu/arm/shared/include/arm-cp15.h
$(PROJECT_INCLUDE)/libcpu/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
index e95bb07..6142a1f 100644
--- a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
+++ b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
@@ -122,8 +122,9 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c
diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
new file mode 100644
index 0000000..bc19cb7
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
@@ -0,0 +1,134 @@
+/**
+ * @file
+ *
+ * @ingroup arm
+ *
+ * @brief ARM cache defines and implementation.
+ */
+
+/*
+ * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rt...@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
+#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
+
+#include <libcpu/arm-cp15.h>
+
+#define CPU_DATA_CACHE_ALIGNMENT 32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
+#if defined(__ARM_ARCH_7A__)
+/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
+#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#endif
+
+static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
+{
+ arm_cp15_data_cache_clean_line(d_addr);
+}
+
+static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+{
+ arm_cp15_data_cache_invalidate_line(d_addr);
+}
+
+static inline void _CPU_cache_freeze_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_unfreeze_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+{
+ arm_cp15_instruction_cache_invalidate_line(d_addr);
+}
+
+static inline void _CPU_cache_freeze_instruction(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_unfreeze_instruction(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_flush_entire_data(void)
+{
+ arm_cp15_data_cache_test_and_clean();
+}
+
+static inline void _CPU_cache_invalidate_entire_data(void)
+{
+ arm_cp15_data_cache_invalidate();
+}
+
+static inline void _CPU_cache_enable_data(void)
+{
+ rtems_interrupt_level level;
+ uint32_t ctrl;
+
+ rtems_interrupt_disable(level);
+ ctrl = arm_cp15_get_control();
+ ctrl |= ARM_CP15_CTRL_C;
+ arm_cp15_set_control(ctrl);
+ rtems_interrupt_enable(level);
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+ rtems_interrupt_level level;
+ uint32_t ctrl;
+
+ rtems_interrupt_disable(level);
+ arm_cp15_data_cache_test_and_clean_and_invalidate();
+ ctrl = arm_cp15_get_control();
+ ctrl &= ~ARM_CP15_CTRL_C;
+ arm_cp15_set_control(ctrl);
+ rtems_interrupt_enable(level);
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void)
+{
+ arm_cp15_instruction_cache_invalidate();
+}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+ rtems_interrupt_level level;
+ uint32_t ctrl;
+
+ rtems_interrupt_disable(level);
+ ctrl = arm_cp15_get_control();
+ ctrl |= ARM_CP15_CTRL_I;
+ arm_cp15_set_control(ctrl);
+ rtems_interrupt_enable(level);
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+ rtems_interrupt_level level;
+ uint32_t ctrl;
+
+ rtems_interrupt_disable(level);
+ ctrl = arm_cp15_get_control();
+ ctrl &= ~ARM_CP15_CTRL_I;
+ arm_cp15_set_control(ctrl);
+ rtems_interrupt_enable(level);
+}
+
+#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */
diff --git a/c/src/lib/libbsp/arm/smdk2410/Makefile.am
b/c/src/lib/libbsp/arm/smdk2410/Makefile.am
index f2bf22d..7ded721 100644
--- a/c/src/lib/libbsp/arm/smdk2410/Makefile.am
+++ b/c/src/lib/libbsp/arm/smdk2410/Makefile.am
@@ -11,6 +11,7 @@ include_HEADERS += smc/smc.h
include_HEADERS += ../../shared/include/tm27.h
include_bsp_HEADERS =
+libbsp_a_CPPFLAGS =
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -64,8 +65,9 @@ libbsp_a_SOURCES += smc/smc.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
../../../libcpu/@RTEMS_CPU@/s3c24xx/clock.rel \
diff --git a/c/src/lib/libcpu/arm/shared/include/cache_.h
b/c/src/lib/libcpu/arm/shared/include/cache_.h
index a31fc11..9db399e 100644
--- a/c/src/lib/libcpu/arm/shared/include/cache_.h
+++ b/c/src/lib/libcpu/arm/shared/include/cache_.h
@@ -3,7 +3,7 @@
*
* @ingroup arm
*
- * @brief ARM cache defines and implementation.
+ * @brief ARM cache dummy include for chips without cache
*/
/*
@@ -23,110 +23,36 @@
#ifndef LIBCPU_ARM_CACHE__H
#define LIBCPU_ARM_CACHE__H
-#ifdef __ARM_ARCH_5TEJ__
- #include <libcpu/arm-cp15.h>
-
- #define CPU_DATA_CACHE_ALIGNMENT 32
- #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
-
- static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
- {
- arm_cp15_data_cache_clean_line(d_addr);
- }
-
- static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
- {
- arm_cp15_data_cache_invalidate_line(d_addr);
- }
-
- static inline void _CPU_cache_freeze_data(void)
- {
- /* TODO */
- }
-
- static inline void _CPU_cache_unfreeze_data(void)
- {
- /* TODO */
- }
-
- static inline void _CPU_cache_invalidate_1_instruction_line(const void
*d_addr)
- {
- arm_cp15_instruction_cache_invalidate_line(d_addr);
- }
-
- static inline void _CPU_cache_freeze_instruction(void)
- {
- /* TODO */
- }
-
- static inline void _CPU_cache_unfreeze_instruction(void)
- {
- /* TODO */
- }
-
- static inline void _CPU_cache_flush_entire_data(void)
- {
- arm_cp15_data_cache_test_and_clean();
- }
-
- static inline void _CPU_cache_invalidate_entire_data(void)
- {
- arm_cp15_data_cache_invalidate();
- }
-
- static inline void _CPU_cache_enable_data(void)
- {
- rtems_interrupt_level level;
- uint32_t ctrl;
-
- rtems_interrupt_disable(level);
- ctrl = arm_cp15_get_control();
- ctrl |= ARM_CP15_CTRL_C;
- arm_cp15_set_control(ctrl);
- rtems_interrupt_enable(level);
- }
-
- static inline void _CPU_cache_disable_data(void)
- {
- rtems_interrupt_level level;
- uint32_t ctrl;
-
- rtems_interrupt_disable(level);
- arm_cp15_data_cache_test_and_clean_and_invalidate();
- ctrl = arm_cp15_get_control();
- ctrl &= ~ARM_CP15_CTRL_C;
- arm_cp15_set_control(ctrl);
- rtems_interrupt_enable(level);
- }
-
- static inline void _CPU_cache_invalidate_entire_instruction(void)
- {
- arm_cp15_instruction_cache_invalidate();
- }
-
- static inline void _CPU_cache_enable_instruction(void)
- {
- rtems_interrupt_level level;
- uint32_t ctrl;
-
- rtems_interrupt_disable(level);
- ctrl = arm_cp15_get_control();
- ctrl |= ARM_CP15_CTRL_I;
- arm_cp15_set_control(ctrl);
- rtems_interrupt_enable(level);
- }
-
- static inline void _CPU_cache_disable_instruction(void)
- {
- rtems_interrupt_level level;
- uint32_t ctrl;
+/*
+ * The ARM targets equipped by cache should include
+ * which kind and implementation they support.
+ * Next options are available
+ *
+ * c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
+ * basic ARM cache integrated on the CPU core directly
+ * which requires only CP15 oparations
+ *
+ * c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+ * support for case where ARM L2C-310 cache controller
+ * is used. It is accessible as mmaped peripheral.
+ *
+ * c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
+ * Cortex-M specific cache support
+ *
+ * Cache support should be included in BSP Makefile.am
+ *
+ * Example how to include cache support
+ *
+ * # Cache
+ * libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+ * libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
+ * libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+ * libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
+ */
- rtems_interrupt_disable(level);
- ctrl = arm_cp15_get_control();
- ctrl &= ~ARM_CP15_CTRL_I;
- arm_cp15_set_control(ctrl);
- rtems_interrupt_enable(level);
- }
+#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__)
+#warning ARM 5TEJ and ARMv7/Cortex-A cores include usually cache
+#warning change BSP to include appropriate cache implementation
#endif
#endif /* LIBCPU_ARM_CACHE__H */
--
1.9.1
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