In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets
loaded back to the CPSR in save_more_context it won't re-enable the FIQs.
Tested on a TMS570LS3137.
---
cpukit/score/cpu/arm/armv4-exception-default.S | 8
1 file changed, 8 insertions(+)
diff --git a/cpuki
Patch attached.
On Thu, Feb 26, 2015 at 5:26 AM, Sebastian Huber
wrote:
> Looks good, can you please send a patch.
>
>
> On 25/02/15 20:57, Martin Galvan wrote:
>>
>> Follow-up from here:
>>
>> https://lists.rtems.org/pipermail/devel/2015-February/009974.html
>>
>> When talking to Sebastian Huber
Looks good, can you please send a patch.
On 25/02/15 20:57, Martin Galvan wrote:
Follow-up from here:
https://lists.rtems.org/pipermail/devel/2015-February/009974.html
When talking to Sebastian Huber about the behavior of
_ARMV4_Exception_fiq_default, he mentioned that it shouldn't re-enable
Follow-up from here:
https://lists.rtems.org/pipermail/devel/2015-February/009974.html
When talking to Sebastian Huber about the behavior of
_ARMV4_Exception_fiq_default, he mentioned that it shouldn't re-enable FIQs
again. This patch sets the F bit of the SPSR so that when it gets loaded back
