Patch attached.
On Thu, Feb 26, 2015 at 5:26 AM, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
> Looks good, can you please send a patch.
>
>
> On 25/02/15 20:57, Martin Galvan wrote:
>>
>> Follow-up from here:
>>
>> https://lists.rtems.org/pipermail/devel/2015-February/009974.html
>>
>> When talking to Sebastian Huber about the behavior of
>> _ARMV4_Exception_fiq_default, he mentioned that it shouldn't re-enable FIQs
>> again. This patch sets the F bit of the SPSR so that when it gets loaded
>> back to the CPSR in save_more_context it won't enable the FIQs.
>>
>> So far I've tested it on the TMS570 and it seems to be working fine (we
>> were getting endless FIQs before, now we end up in bsp_reset). However, I'm
>> not sure if there are other BSPs out there that rely on the previous
>> behavior.
>>
>> diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S
>> b/cpukit/score/cpu/arm/armv4-exception-default.S
>> index a0ee46c..a10de30 100644
>> --- a/cpukit/score/cpu/arm/armv4-exception-default.S
>> +++ b/cpukit/score/cpu/arm/armv4-exception-default.S
>> @@ -99,6 +99,14 @@ _ARMV4_Exception_fiq_default:
>> stmdb sp!, {r0-r12}
>> mov r4, #7
>>
>> + /*
>> + * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
>> + * (which we'll load into the CPSR in save_more_context).
>> + */
>> + mrs r2, spsr
>> + orr r2, #ARM_PSR_F
>> + msr spsr_c, r2
>> +
>> save_more_context:
>>
>> /* Save more context */
>
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone : +49 89 189 47 41-16
> Fax : +49 89 189 47 41-09
> E-Mail : sebastian.hu...@embedded-brains.de
> PGP : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
--
Martín Galván
Software Engineer
Taller Technologies Argentina
San Lorenzo 47, 3rd Floor, Office 5
Córdoba, Argentina
Phone: 54 351 4217888 / +54 351 4218211
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S
index a0ee46c..a10de30 100644
--- a/cpukit/score/cpu/arm/armv4-exception-default.S
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -99,6 +99,14 @@ _ARMV4_Exception_fiq_default:
stmdb sp!, {r0-r12}
mov r4, #7
+ /*
+ * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
+ * (which we'll load into the CPSR in save_more_context).
+ */
+ mrs r2, spsr
+ orr r2, #ARM_PSR_F
+ msr spsr_c, r2
+
save_more_context:
/* Save more context */
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