In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets
loaded back to the CPSR in save_more_context it won't re-enable the FIQs.
Tested on a TMS570LS3137.
---
cpukit/score/cpu/arm/armv4-exception-default.S | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S
b/cpukit/score/cpu/arm/armv4-exception-default.S
index a0ee46c..a10de30 100644
--- a/cpukit/score/cpu/arm/armv4-exception-default.S
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -99,6 +99,14 @@ _ARMV4_Exception_fiq_default:
stmdb sp!, {r0-r12}
mov r4, #7
+ /*
+ * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
+ * (which we'll load into the CPSR in save_more_context).
+ */
+ mrs r2, spsr
+ orr r2, #ARM_PSR_F
+ msr spsr_c, r2
+
save_more_context:
/* Save more context */
--
2.3.0
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