On 04/07/2016 15:46, Sebastian Huber wrote:
On 03/07/16 06:56, Chris Johns wrote:
On 30/06/2016 20:22, Deval Shah wrote:
On Tue, Jun 28, 2016 at 3:12 AM, Chris Johns mailto:chr...@rtems.org>> wrote:
It might pay for us to add these to an RTEMS header to make porting
simpler.
Can't we
On 03/07/16 06:56, Chris Johns wrote:
On 30/06/2016 20:22, Deval Shah wrote:
On Tue, Jun 28, 2016 at 3:12 AM, Chris Johns mailto:chr...@rtems.org>> wrote:
It might pay for us to add these to an RTEMS header to make porting
simpler.
Can't we update our sys/net/if.c and sys/net/if_var.h
On 04/07/16 01:52, pp...@cmp.felk.cvut.cz wrote:
From: Pavel Pisa
When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next opt
On 04/07/16 01:52, pp...@cmp.felk.cvut.cz wrote:
+#if defined(__ARM_ARCH_7A__)
+ #define ARM_MULTILIB_CACHE_LINE_MAX_64B
+#endif
Is 'B' bytes or bits? I think in the cache line context its pretty
clear that these are bytes, so I would use
ARM_MULTILIB_CACHE_LINE_MAX_64
or
ARM_MULTILIB_
Does it make sense to use the new
ARM_MULTILIB_CACHE_LINE_MAX_64B
here?
On 04/07/16 01:52, pp...@cmp.felk.cvut.cz wrote:
From: Pavel Pisa
---
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4
1 file changed, 4 insertions(+)
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/c
From: Pavel Pisa
Synchronize each cluster of sections of the same type separately
to support even cases where text and data are allocated from different
areas (for example due allocation from different MPU protection regions).
rtems_cache_instruction_sync_after_code_change is called even to data
From: Pavel Pisa
The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be special
From: Pavel Pisa
When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET([BSP_S
From: Pavel Pisa
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used f
From: Pavel Pisa
This support is required when newer firmware is used on
Raspberry Pi 2 boards.
---
c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 3 +++
c/src/lib/libbsp/arm/raspberrypi/configure.ac | 4
2 files changed, 7 insertions(+)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/Makef
From: Pavel Pisa
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
---
c/src/lib/libcpu/arm/
From: Pavel Pisa
The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2,
clean by individual lines works on RPi1 and RPi2.
---
c/src/lib/libbsp/arm/raspberrypi/misc/vc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/c/src/lib/libbsp/arm/raspberr
From: Pavel Pisa
These changes allows to boot Raspberry Pi 2 with recent firmware
which start system in ARM hypervisor (HYP) mode.
There are more changes to correct/make compile cache manager
functions for more boards (till now only Zynq, Altera Cyclone
and LPC32xx have non empty implementation
From: Pavel Pisa
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
---
cpukit/score/cpu/arm/rtems/score/arm.h | 4
cpukit/score/cpu/arm/rtems/score/cpu.h | 7 +--
2 files changed, 9 insertions(+), 2 deletions(
From: Pavel Pisa
---
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4
1 file changed, 4 insertions(+)
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 35c8002..e83b55c 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l
From: Pavel Pisa
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basi
Hello everybody,
I have managed HYP boot to run on RPi2 even when application
is loaded by U-boot. Code is functional on RPi1 in SVC
boot mode and U-boot load with cache enabled and should
work even with direct boots from (hopefully) all versions
of firmware. Graphic works on RPi1 and on RPi2 unde
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