@@ -18,7 +18,7 @@
// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
// CHECK-CXX-NEXT:ret void
//
-void test_svzero_mask_za() {
+__arm_new_za void test_svzero_mask_za() {
sdesmalen-arm wrote:
Why are these `__arm_new_za` rather than `__arm
@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
di
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@@ -1,13 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
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@@ -449,6 +452,9 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper
&Records) {
case GenArmFP16:
EmitFP16(Records, OS);
break;
+ case GenArmVectorType:
+EmitVectorType(Records, OS);
sdesmalen-arm wrote:
nit: please use "Types" (plural) ins
@@ -1,5 +1,4 @@
// RUN: %clang_cc1 %s -triple armv7 -fsyntax-only -verify
-typedef __attribute__((neon_vector_type(2))) int int32x2_t; //
expected-error{{'neon_vector_type' attribute is not supported on targets
missing 'neon' or 'mve'; specify an appropriate -march= or -mcpu=
@@ -2355,13 +2357,7 @@ void NeonEmitter::run(raw_ostream &OS) {
OS << "#include \n";
- // Emit NEON-specific scalar typedefs.
- OS << "typedef float float32_t;\n";
- OS << "typedef __fp16 float16_t;\n";
-
- OS << "#ifdef __aarch64__\n";
- OS << "typedef double float64_
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-ll
@@ -1970,17 +1969,23 @@ def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]",
"dd$$i", "f", MergeNone, "aar
let TargetGuard = "sve2p1" in {
def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone,
"aarch64_sve_sclamp", [], []>;
def SVUCLAMP : SInst<"svclamp[_{d}]", "
@@ -508,6 +508,9 @@ def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64",
"HasSMEI16I64", "true",
def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
"Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
+def FeatureSMEFA64 : Su
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https://github.com/sdesmalen-arm approved this pull request.
LGTM with nit addressed
https://github.com/llvm/llvm-project/pull/70809
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https://github.com/sdesmalen-arm approved this pull request.
Thanks for all the changes! LGTM with few little nits addressed.
https://github.com/llvm/llvm-project/pull/68565
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@@ -4850,6 +4852,93 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+// Case 1: If the vector number (vecnum) is an immediate in range, it gets
+//
@@ -4850,6 +4852,93 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+// Case 1: If the vector number (vecnum) is an immediate in range, it gets
+//
@@ -4850,6 +4852,93 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
sdesmalen-arm wrote:
```suggestion
// Lower an SME LDR/STR ZA
@@ -1970,17 +1969,20 @@ def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]",
"dd$$i", "f", MergeNone, "aar
let TargetGuard = "sve2p1" in {
def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone,
"aarch64_sve_sclamp", [], []>;
def SVUCLAMP : SInst<"svclamp[_{d}]", "
@@ -1992,3 +1986,12 @@ let TargetGuard = "sme2" in {
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNon
https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/72979
>From ffc1922935f6c5e9fc66db7fcce72ad0f5d8bef8 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Tue, 21 Nov 2023 13:50:33 +
Subject: [PATCH] [llvm][TypeSize] Fix addition/subtraction in TypeSize.
https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/72994
>From ffc1922935f6c5e9fc66db7fcce72ad0f5d8bef8 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Tue, 21 Nov 2023 13:50:33 +
Subject: [PATCH 1/2] [llvm][TypeSize] Fix addition/subtraction in TypeSiz
https://github.com/sdesmalen-arm edited
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sdesmalen-arm wrote:
> Creating a scalable vector of size 0 should not even be allowed.
Correct, but that is no reason to disallow a value of '0' for TypeSize. This is
just a class to represent a value (fixed or scalable), and it's up to the
places where TypeSize is used on whether that use is
https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/72979
>From ffc1922935f6c5e9fc66db7fcce72ad0f5d8bef8 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Tue, 21 Nov 2023 13:50:33 +
Subject: [PATCH 1/2] [llvm][TypeSize] Fix addition/subtraction in TypeSiz
sdesmalen-arm wrote:
Thanks @paulwalker-arm @gchatelet!
https://github.com/llvm/llvm-project/pull/72979
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sdesmalen-arm wrote:
> Also, you might want to consider marking the offset immarg, instead of trying
> to handle variable offsets in isel.
`vnum` doesn't need to be an immediate in the C/C++ intrinsic, so it makes
sense to just pass it onto LLVM so that ISel can try to fold it into the
immedi
@@ -1741,6 +1742,54 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
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@@ -1741,6 +1742,54 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -1741,6 +1742,54 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -1741,6 +1742,54 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -805,16 +805,16 @@ multiclass sme_fill {
MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4,
GPR64sp:$Rn, 0), 1>;
def NAME # _PSEUDO
: Pseudo<(outs),
- (ins MatrixIndexGPR32Op12_15:$idx, imm0_15:$imm4,
+ (ins MatrixInde
@@ -9893,24 +9888,40 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
@@ -9893,24 +9888,40 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
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@@ -491,13 +491,13 @@ bool AArch64Subtarget::isStreamingCompatible() const {
}
bool AArch64Subtarget::isNeonAvailable() const {
- return hasNEON() && !isStreaming() && !isStreamingCompatible();
+ return (hasNEON() || hasSMEFA64()) && !isStreaming() &&
sdesma
@@ -248,8 +250,9 @@ inline constexpr ExtensionInfo Extensions[] = {
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD,
"+fp-armv8,+neon", 100},
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4,
"+sm4,+fp-armv8,+neon", 60},
{"sme-f16f16", AArch64::AEK_SMEF1
@@ -508,6 +508,9 @@ def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64",
"HasSMEI16I64", "true",
def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
"Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
+def FeatureSMEFA64 : Su
@@ -2,6 +2,8 @@
// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -m
@@ -9924,12 +9917,56 @@ Value
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
// immediate requires more than a handful of bits.
*Result = Result->extOrTrunc(32);
Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), *Result));
+ continu
@@ -9924,12 +9917,56 @@ Value
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
// immediate requires more than a handful of bits.
*Result = Result->extOrTrunc(32);
Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), *Result));
+ continu
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@@ -1133,6 +1133,9 @@ typedef struct __ifunc_arg_t {
#ifndef HWCAP2_SME_F64F64
#define HWCAP2_SME_F64F64 (1 << 25)
#endif
+#ifndef HWCAP2_SME_FA64
+#define HWCAP2_SME_FA64 (1 << 26)
sdesmalen-arm wrote:
Where did you get the `1 << 26` from? I think it should b
@@ -491,13 +491,15 @@ bool AArch64Subtarget::isStreamingCompatible() const {
}
bool AArch64Subtarget::isNeonAvailable() const {
- return hasNEON() && !isStreaming() && !isStreamingCompatible();
+ if (hasSMEFA64())
+return true;
+ return (hasNEON() && !isStreaming() && !
@@ -491,13 +491,15 @@ bool AArch64Subtarget::isStreamingCompatible() const {
}
bool AArch64Subtarget::isNeonAvailable() const {
- return hasNEON() && !isStreaming() && !isStreamingCompatible();
+ if (hasSMEFA64())
+return true;
+ return (hasNEON() && !isStreaming() && !
@@ -1224,7 +1233,27 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
- OS << "#include \n";
+ OS << "#include \n\n";
+
+ OS << "typedef __attribute__((vector_size (16))) int8_t __sve_int8x16_t;\n";
sdesm
@@ -0,0 +1,285 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %cla
https://github.com/sdesmalen-arm approved this pull request.
This patch was reviewed as part of PR #70662, so I'm happy for this patch to
reland.
https://github.com/llvm/llvm-project/pull/70959
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h
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mattr=+sve -mattr=+sme-fa64 -force-streaming-compatible-sve < %s |
FileCheck %s -check-prefix=FA64
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck
@@ -162,6 +163,7 @@ enum ArchExtKind : unsigned {
AEK_FPMR = 58, // FEAT_FPMR
AEK_FP8 = 59, // FEAT_FP8
AEK_FAMINMAX = 60, // FEAT_FAMINMAX
+ AEK_SMEFA64 = 61, // FEAT_SMEFA64
sdesmalen-arm wrote:
nit: can you define this a
@@ -508,6 +508,9 @@ def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64",
"HasSMEI16I64", "true",
def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
"Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
+def FeatureSMEFA64 : Su
@@ -248,8 +250,9 @@ inline constexpr ExtensionInfo Extensions[] = {
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD,
"+fp-armv8,+neon", 100},
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4,
"+sm4,+fp-armv8,+neon", 60},
{"sme-f16f16", AArch64::AEK_SMEF1
@@ -292,23 +292,101 @@ define void @ldr_with_off_16mulvl(ptr %ptr) {
%vscale = call i64 @llvm.vscale.i64()
%mulvl = mul i64 %vscale, 256
%base = getelementptr i8, ptr %ptr, i64 %mulvl
- call void @llvm.aarch64.sme.ldr(i32 16, ptr %base)
+ call void @llvm.aarch64.sme.ldr
@@ -4825,6 +4827,72 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -4825,6 +4827,72 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -4825,6 +4827,72 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -1744,45 +1744,60 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
- // If the vector select parameter is a
@@ -4825,6 +4827,72 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -2355,13 +2357,7 @@ void NeonEmitter::run(raw_ostream &OS) {
OS << "#include \n";
- // Emit NEON-specific scalar typedefs.
- OS << "typedef float float32_t;\n";
- OS << "typedef __fp16 float16_t;\n";
-
- OS << "#ifdef __aarch64__\n";
- OS << "typedef double float64_
@@ -8360,9 +8360,11 @@ static void HandleNeonVectorTypeAttr(QualType &CurType,
const ParsedAttr &Attr,
// not to need a separate attribute)
if (!(S.Context.getTargetInfo().hasFeature("neon") ||
S.Context.getTargetInfo().hasFeature("mve") ||
+S.Context.getTa
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https://github.com/llvm/llvm-project/pull/73258
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@@ -1694,6 +1697,61 @@ void SVEEmitter::createSMERangeChecks(raw_ostream &OS) {
OS << "#endif\n\n";
}
+void SVEEmitter::createStreamingAttrs(raw_ostream &OS, ACLEKind Kind) {
+ std::vector RV = Records.getAllDerivedDefinitions("Inst");
+ SmallVector, 128> Defs;
+ for (aut
@@ -3168,9 +3167,60 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
dia
@@ -3168,9 +3167,60 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
dia
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sdesmalen-arm wrote:
> On my system, this increases the compilation time of SemaChecking.cpp from 7
> seconds to 2 minutes 46 seconds (using clang as a host compiler). That seems
> excessive. Let's please find a way to not make compilation so slow, and let's
> consider reverting this until a f
@@ -8,6 +8,14 @@
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-fe
@@ -148,10 +151,10 @@ void test_svpmov_lane(){
svuint64_t zn_u64;
svbool_t pn;
- svpmov_lane_u8(zn_u8, -1); // expected-error {{argument value -1 is outside
the valid range [0, 0]}}
- svpmov_lane_u16(zn_u16, -1); // expected-error {{argument value -1 is
outside the val
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
@@ -8,6 +8,14 @@
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-fe
@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
--
@@ -315,6 +315,223 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
sdesmalen-arm wrote:
> > If it's not too much trouble, could you `git cherry-pick
> > c60663d128f8e0dccd418bdf16ecc403b96aa74a` into this? (Cool if not, ofc.)
>
> Sure, I can do that. Would you also mind attempting to reproduce the compile
> time with the latest commit, just to make sure it fi
@@ -1702,6 +1705,62 @@ void SVEEmitter::createSMERangeChecks(raw_ostream &OS) {
OS << "#endif\n\n";
}
+void SVEEmitter::createStreamingAttrs(raw_ostream &OS, ACLEKind Kind) {
+ std::vector RV = Records.getAllDerivedDefinitions("Inst");
+ SmallVector, 128> Defs;
+ for (aut
@@ -8,6 +8,8 @@
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-fea
@@ -2,7 +2,10 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-ll
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/72487
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https://github.com/sdesmalen-arm approved this pull request.
Assuming the tests pass after changing `BuiltinType` to a `std::optional`, the
patch looks fine to me.
https://github.com/llvm/llvm-project/pull/75487
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https://github.com/sdesmalen-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/75200
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https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/75200
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@@ -1,12 +1,21 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
https://github.com/sdesmalen-arm created
https://github.com/llvm/llvm-project/pull/75791
This includes:
* __arm_in_streaming_mode()
* __arm_has_sme()
* __arm_za_disable()
* __svundef_za()
>From 8b30f772982d7d608541526b1fa42de2b5eb7e1e Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Mon,
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/74841
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https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/75805
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https://github.com/sdesmalen-arm approved this pull request.
LGTM with comment addressed.
https://github.com/llvm/llvm-project/pull/71927
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@@ -2,13 +2,24 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+/
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/71927
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https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/75791
>From 8b30f772982d7d608541526b1fa42de2b5eb7e1e Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Mon, 18 Dec 2023 12:55:30 +
Subject: [PATCH 1/2] [Clang][AArch64] Add missing SME functions to header
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/71927
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@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -313,6 +313,72 @@ let TargetGuard = "sme2" in {
def SVBMOPA : Inst<"svbmopa_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNo
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