https://github.com/BeMg approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/74889
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BeMg wrote:
> LGTM
>
> Related question. If there is an -mcpu on the command line and target
> attribute changes the march, do we keep the original CPU in the -target-cpu
> attribute or drop it. The reason for all those negative features from the
> driver was to make the backend not infer any
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/75804
Address question from https://github.com/llvm/llvm-project/pull/74889
---
The target-cpu will infer its target-feature during backend codegen, it will
make TargetAttr doesn't work.
This patch implement the followi
Author: Piyou Chen
Date: 2023-11-23T23:05:21-08:00
New Revision: d80e46da7d20645afd7b751a4e6cba9837addcb4
URL:
https://github.com/llvm/llvm-project/commit/d80e46da7d20645afd7b751a4e6cba9837addcb4
DIFF:
https://github.com/llvm/llvm-project/commit/d80e46da7d20645afd7b751a4e6cba9837addcb4.diff
LO
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/75804
>From 139ab4d26badc0d43c14fc94fe73db32342cfc1e Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 17 Dec 2023 23:12:12 -0800
Subject: [PATCH 1/2] Make target-cpu override rule correct
---
clang/lib/CodeGen/CodeGe
https://github.com/BeMg approved this pull request.
https://github.com/llvm/llvm-project/pull/76962
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https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/85786
This patch enable the function multiversion(FMV) and `target_clones` attribute
for RISC-V target.
It will emit the IFUNC resolver function to select appropriate function during
runtime.
>From 239b404203c66ab5336f
BeMg wrote:
Inside the resolver function, a function named `__riscv_ifunc_select` is used
to ensure that all additional extension requirements are met. It is temporary
interface until proposal be ratified.
```
bool __riscv_ifunc_select(char *FeatureStr);
```
https://github.com/llvm/llvm-proj
BeMg wrote:
The candidate function priority order is undefined. Currently, it base on
declaration order.
https://github.com/llvm/llvm-project/pull/85786
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BeMg wrote:
The warning occurs because the RISC-V target_clones syntax
`__attribute__((target_clones("default", "arch=+zba,+v,+c,+zicond",
"arch=+zbb,+c,+v")))` contains a comma inside double quotes.
```
warning: mixing 'target_clones' specifier mechanisms is permitted for GCC
compatibility;
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/85899
For RISC-V target only `target_clones` and `target_version` can enable function
multiversion(FMV).
This patch make target attribute trigger redefinition instead of emit FMV.
>From 0bbffb92e7f36957c042cab9a67a48357
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/2] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/T
https://github.com/BeMg ready_for_review
https://github.com/llvm/llvm-project/pull/85786
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BeMg wrote:
The proposal can be found at the
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48.
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/llvm/llvm-project/pull/85899
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BeMg wrote:
The proposal could be found here
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48.
https://github.com/llvm/llvm-project/pull/85899
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/4] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/T
BeMg wrote:
1. Suppress the warning `warn_target_clone_mixed_values` for RISC-V
2. Update `__riscv_ifunc_select`. From `__riscv_ifunc_select(char *)` into
`__riscv_ifunc_select(unsigned long long, unsigned long long )`.
3. Add one more error messenge when there are +extension that hwprobe can't
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85899
>From 0bbffb92e7f36957c042cab9a67a483571d9b3f9 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH 1/2] [RISCV] Disallow target attribute use in multiversioning
---
clang
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
BeMg wrote:
This code section will make clang vio
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/83674
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@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include
+
+void test_builtin() {
+ __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_r
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/7] [RISCV] Relax march string order constraint
---
clang/test/Driver/
@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitExts) {
+ SmallVector Split;
+ if (Exts.empty())
+retu
@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitExts) {
+ SmallVector Split;
+ if (Exts.empty())
+retu
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/7] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 7ad5726d93e957050723a7df7a8384bc9ff694b3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/8] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 7ad5726d93e957050723a7df7a8384bc9ff694b3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From aaee7cfdea325459d68bc4e7205d7e25ca045d1a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 8f7b429d2f7fe791a2a469e3d232d33abba1bef8 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From f3444e9f434a5084b16ad25981428549c5b2e151 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/78120
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https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/78120
Address the https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14
This patch relax the `-march` string for accept any order.
1. single-letter extension can be arbitrary order
- march=rv32iamdf
2
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/4] [RISCV] Relax march string order constraint
---
clang/test/Driver/
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/78120
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@@ -785,153 +878,61 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
Minor = Version->Minor;
}
-ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor});
+// Postpone AddExtension until end of this function
+SeenEx
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32I
@@ -337,10 +319,79 @@ TEST(ParseArchString,
AcceptsUnderscoreSplittingExtensions) {
}
}
+TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) {
+ for (StringRef Input :
+ {"rv32imfad", "rv32im_fa_d", "rv32im2p0fad", "rv32i2p1m2p0fad"}) {
+auto MaybeISAInfo =
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/6] [RISCV] Relax march string order constraint
---
clang/test/Driver/
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
BeMg wrote:
Done
https://github
@@ -715,6 +815,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
unsigned XLen = HasRV64 ? 64 : 32;
std::unique_ptr ISAInfo(new RISCVISAInfo(XLen));
+ SmallVector SeenExts;
BeMg wrote:
Use MapVector instead of SmallVec
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/75804
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BeMg wrote:
Close due to land https://github.com/llvm/llvm-project/pull/77426
https://github.com/llvm/llvm-project/pull/75804
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Author: Piyou Chen
Date: 2022-10-24T01:27:04-07:00
New Revision: f8b8426861a7a26ff60fe085800cc338591bee41
URL:
https://github.com/llvm/llvm-project/commit/f8b8426861a7a26ff60fe085800cc338591bee41
DIFF:
https://github.com/llvm/llvm-project/commit/f8b8426861a7a26ff60fe085800cc338591bee41.diff
LO
Author: Piyou Chen
Date: 2022-10-26T09:45:30-07:00
New Revision: 7d7940fd7761e21b68f915e948389b87835d1304
URL:
https://github.com/llvm/llvm-project/commit/7d7940fd7761e21b68f915e948389b87835d1304
DIFF:
https://github.com/llvm/llvm-project/commit/7d7940fd7761e21b68f915e948389b87835d1304.diff
LO
Author: Piyou Chen
Date: 2022-12-20T01:13:13-08:00
New Revision: 0d4c6506100b339311283c10d841d7693287666a
URL:
https://github.com/llvm/llvm-project/commit/0d4c6506100b339311283c10d841d7693287666a
DIFF:
https://github.com/llvm/llvm-project/commit/0d4c6506100b339311283c10d841d7693287666a.diff
LO
Author: Piyou Chen
Date: 2022-12-21T20:28:12-08:00
New Revision: 5370255ff18ac101a73685b77615148142ee7552
URL:
https://github.com/llvm/llvm-project/commit/5370255ff18ac101a73685b77615148142ee7552
DIFF:
https://github.com/llvm/llvm-project/commit/5370255ff18ac101a73685b77615148142ee7552.diff
LO
Author: Piyou Chen
Date: 2023-08-04T00:39:25-07:00
New Revision: 2df05cd01c17f3ef720e554dc7cde43df27e5224
URL:
https://github.com/llvm/llvm-project/commit/2df05cd01c17f3ef720e554dc7cde43df27e5224
DIFF:
https://github.com/llvm/llvm-project/commit/2df05cd01c17f3ef720e554dc7cde43df27e5224.diff
LO
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/65948:
The spec of RISC-V target feature is
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35.
---
This patch implements target attribute for RISC-V.
>From 4e661a7cc4775e569bd648b0a119ece51ec031f7 Mon Sep 17 00:0
https://github.com/BeMg review_requested
https://github.com/llvm/llvm-project/pull/65948
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BeMg wrote:
This pull request move from https://reviews.llvm.org/D151730.
And update with lastest spec.
1. When it exist the duplicate target attribute, select the lastest one.
2. arch's features will override cpu's features
https://github.com/llvm/llvm-project/pull/65948
Author: Piyou Chen
Date: 2023-04-24T23:14:56-07:00
New Revision: dc72e8fe675866b93748d54bc5e04b14c675f476
URL:
https://github.com/llvm/llvm-project/commit/dc72e8fe675866b93748d54bc5e04b14c675f476
DIFF:
https://github.com/llvm/llvm-project/commit/dc72e8fe675866b93748d54bc5e04b14c675f476.diff
LO
BeMg wrote:
Support `priority` syntax for target_version
https://github.com/llvm/llvm-project/pull/99040
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BeMg wrote:
stack on https://github.com/llvm/llvm-project/pull/85786
https://github.com/llvm/llvm-project/pull/99040
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https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/16] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
BeMg wrote:
ping
https://github.com/llvm/llvm-project/pull/106495
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/106495
>From e8f472674e0d1e70adcd1d29b8c902f4cd80f188 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 28 Aug 2024 21:15:57 -0700
Subject: [PATCH 1/7] [Clang][RISCV] Recognize unsupport feature by supporting
isValidFe
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
st
@@ -2993,10 +2993,17 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
- if (Context.getTargetInfo().getTriple().isRI
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
st
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
st
BeMg wrote:
> A test case will crash, missing `+` before `zbc`:
>
> ```
> __attribute__((target_clones("default", "arch=+zbb,zbc;priority=-1",
> "priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo1(void) {
> return 2; }
>
>
> int bar() { return foo1(); }
> ```
>
> ```
> $ clang
BeMg wrote:
Rename and update the description of err_os_unsupport_riscv_target_clones
because not only target clones trigger FMV.
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/106495
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@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RI
@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClones
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/101472
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/6] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/T
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85899
>From 0bbffb92e7f36957c042cab9a67a483571d9b3f9 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH 1/3] [RISCV] Disallow target attribute use in multiversioning
---
clang
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 01/10] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85899
>From 894c0975638a99c84fde8d1ea5c845e5cdbf32f4 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH 1/3] [RISCV] Disallow target attribute use in multiversioning
---
clang
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 01/11] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85899
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https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/85899
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 48eea6eda33c4e73316fe938a15d8e361039072e Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/2] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
BeMg wrote:
Stack on https://github.com/llvm/llvm-project/pull/94440
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg approved this pull request.
LGTM. Work fine with current compiler-rt `__init_riscv_feature_bits
`/`__riscv_feature_bits ` and qemu with hwprobe support.
https://github.com/llvm/llvm-project/pull/99700
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https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/99700
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 708c81609c603c5ea820493e92d8c82cf4620d64 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 1/3] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticF
BeMg wrote:
> @BeMg Can you rebase over commit
> [d1e28e2](https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59)?
Now this patch rebase over
https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59.
Majorly, the diff between origin p
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786
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BeMg wrote:
> > The proposal can be found at the
> > [riscv-non-isa/riscv-c-api-doc#48](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48).
>
> Please put this in the PR description
Updated PR description
https://github.com/llvm/llvm-project/pull/85786
_
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/5] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/6] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 01/10] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://g
@@ -3127,6 +3142,32 @@ bool Sema::checkTargetClonesAttrString(
/*IncludeLocallyStreaming=*/false))
return Diag(LiteralLoc,
diag::err_sme_streaming_cannot_be_multiversioned);
+} else if (TInfo.getTriple().isRISCV()
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 4260683c6d589bc5a64ceffd5e409336f81d85eb Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/3] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 4260683c6d589bc5a64ceffd5e409336f81d85eb Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/5] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
@@ -0,0 +1,8 @@
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -emit-llvm -o - %s
2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-OS: error: target_clones is currently only supported on
Linux
BeMg wrote:
Added.
https://g
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64
@@ -62,6 +62,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
BeMg wrote:
`RISCVT
BeMg wrote:
> * Updating clang tests to exercise this logic.
> * Actually running it at all. I did not build compiler-rt, and thus all my
> checking was of generated asm/IR.
Maybe we could compile the test code with
`compiler-rt/lib/builtins/riscv/feature_bits.c` manually. Then we could get r
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
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