https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001 From: Piyou Chen <piyou.c...@sifive.com> Date: Wed, 5 Jun 2024 01:17:03 -0700 Subject: [PATCH 1/6] [RISCV] Add groupid/bitmask for RISC-V extension Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74. This patch defines the groupid/bitmask in RISCVFeatures.td and generates the corresponding table in RISCVTargetParserDef.inc. The groupid/bitmask of extensions provides an abstraction layer between the compiler and runtime functions. --- .../llvm/TargetParser/RISCVTargetParser.h | 8 ++ llvm/lib/Target/RISCV/RISCVFeatures.td | 131 ++++++++++++------ llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 +++++ llvm/test/TableGen/riscv-target-def.td | 18 ++- llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 37 +++++ 5 files changed, 183 insertions(+), 43 deletions(-) diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index 5b1494efe7bdc..e998bc4ca59ee 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -24,6 +24,14 @@ class Triple; namespace RISCV { +namespace RISCVExtensionBitmaskTable { +struct RISCVExtensionBitmask { + const char *Name; + unsigned GroupID; + unsigned BitPosition; +}; +} // namespace RISCVExtensionBitmaskTable + // We use 64 bits as the known part in the scalable vector types. static constexpr unsigned RVVBitsPerBlock = 64; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d3cb2aeab41cb..125e9e2f53953 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -37,6 +37,15 @@ class RISCVExtension<string name, int major, int minor, string desc, bit Experimental = false; } +// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value +// from __riscv_feature_bit based on the groupID and bitmask. +// groupID - groupID of extension +// bitmaskShift - bitmask shift of extension +class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> { + int GroupID = groupID; + int BitPos = bitmaskShift; +} + // Version of RISCVExtension to be used for Experimental extensions. This // sets the Experimental flag and prepends experimental- to the -mattr name. class RISCVExperimentalExtension<string name, int major, int minor, string desc, @@ -52,7 +61,8 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc, def FeatureStdExtI : RISCVExtension<"i", 2, 1, - "'I' (Base Integer Instruction Set)">; + "'I' (Base Integer Instruction Set)">, + RISCVExtensionBitmask<0, 8>; def FeatureStdExtE : RISCVExtension<"e", 2, 0, @@ -78,7 +88,8 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, def FeatureStdExtZicboz : RISCVExtension<"zicboz", 1, 0, - "'Zicboz' (Cache-Block Zero Instructions)">; + "'Zicboz' (Cache-Block Zero Instructions)">, + RISCVExtensionBitmask<0, 37>; def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, AssemblerPredicate<(all_of FeatureStdExtZicboz), "'Zicboz' (Cache-Block Zero Instructions)">; @@ -113,7 +124,8 @@ def FeatureStdExtZicntr def FeatureStdExtZicond : RISCVExtension<"zicond", 1, 0, - "'Zicond' (Integer Conditional Operations)">; + "'Zicond' (Integer Conditional Operations)">, + RISCVExtensionBitmask<0, 38>; def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, AssemblerPredicate<(all_of FeatureStdExtZicond), "'Zicond' (Integer Conditional Operations)">; @@ -134,7 +146,8 @@ def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, def FeatureStdExtZihintntl : RISCVExtension<"zihintntl", 1, 0, - "'Zihintntl' (Non-Temporal Locality Hints)">; + "'Zihintntl' (Non-Temporal Locality Hints)">, + RISCVExtensionBitmask<0, 39>; def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, AssemblerPredicate<(all_of FeatureStdExtZihintntl), "'Zihintntl' (Non-Temporal Locality Hints)">; @@ -181,7 +194,8 @@ def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">, def FeatureStdExtM : RISCVExtension<"m", 2, 0, "'M' (Integer Multiplication and Division)", - [FeatureStdExtZmmul]>; + [FeatureStdExtZmmul]>, + RISCVExtensionBitmask<0, 12>; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, AssemblerPredicate<(all_of FeatureStdExtM), "'M' (Integer Multiplication and Division)">; @@ -190,14 +204,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, def FeatureStdExtA : RISCVExtension<"a", 2, 1, - "'A' (Atomic Instructions)">; + "'A' (Atomic Instructions)">, + RISCVExtensionBitmask<0, 0>; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, AssemblerPredicate<(all_of FeatureStdExtA), "'A' (Atomic Instructions)">; def FeatureStdExtZtso : RISCVExtension<"ztso", 1, 0, - "'Ztso' (Memory Model - Total Store Order)">; + "'Ztso' (Memory Model - Total Store Order)">, + RISCVExtensionBitmask<0, 47>; def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, AssemblerPredicate<(all_of FeatureStdExtZtso), "'Ztso' (Memory Model - Total Store Order)">; @@ -227,7 +243,8 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">, def FeatureStdExtZacas : RISCVExtension<"zacas", 1, 0, - "'Zacas' (Atomic Compare-And-Swap Instructions)">; + "'Zacas' (Atomic Compare-And-Swap Instructions)">, + RISCVExtensionBitmask<0, 26>; def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, AssemblerPredicate<(all_of FeatureStdExtZacas), "'Zacas' (Atomic Compare-And-Swap Instructions)">; @@ -264,7 +281,8 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, def FeatureStdExtF : RISCVExtension<"f", 2, 2, "'F' (Single-Precision Floating-Point)", - [FeatureStdExtZicsr]>; + [FeatureStdExtZicsr]>, + RISCVExtensionBitmask<0, 5>; def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, AssemblerPredicate<(all_of FeatureStdExtF), "'F' (Single-Precision Floating-Point)">; @@ -272,7 +290,8 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, def FeatureStdExtD : RISCVExtension<"d", 2, 2, "'D' (Double-Precision Floating-Point)", - [FeatureStdExtF]>; + [FeatureStdExtF]>, + RISCVExtensionBitmask<0, 3>; def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; @@ -280,7 +299,8 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, def FeatureStdExtZfhmin : RISCVExtension<"zfhmin", 1, 0, "'Zfhmin' (Half-Precision Floating-Point Minimal)", - [FeatureStdExtF]>; + [FeatureStdExtF]>, + RISCVExtensionBitmask<0, 36>; def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, AssemblerPredicate<(all_of FeatureStdExtZfhmin), "'Zfh' (Half-Precision Floating-Point) or " @@ -289,7 +309,8 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, def FeatureStdExtZfh : RISCVExtension<"zfh", 1, 0, "'Zfh' (Half-Precision Floating-Point)", - [FeatureStdExtZfhmin]>; + [FeatureStdExtZfhmin]>, + RISCVExtensionBitmask<0, 35>; def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, AssemblerPredicate<(all_of FeatureStdExtZfh), "'Zfh' (Half-Precision Floating-Point)">; @@ -313,7 +334,8 @@ def HasHalfFPLoadStoreMove def FeatureStdExtZfa : RISCVExtension<"zfa", 1, 0, "'Zfa' (Additional Floating-Point)", - [FeatureStdExtF]>; + [FeatureStdExtF]>, + RISCVExtensionBitmask<0, 34>; def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">, AssemblerPredicate<(all_of FeatureStdExtZfa), "'Zfa' (Additional Floating-Point)">; @@ -356,7 +378,8 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">; def FeatureStdExtC : RISCVExtension<"c", 2, 0, - "'C' (Compressed Instructions)">; + "'C' (Compressed Instructions)">, + RISCVExtensionBitmask<0, 2>; def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, AssemblerPredicate<(all_of FeatureStdExtC), "'C' (Compressed Instructions)">; @@ -445,7 +468,8 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, def FeatureStdExtZba : RISCVExtension<"zba", 1, 0, - "'Zba' (Address Generation Instructions)">; + "'Zba' (Address Generation Instructions)">, + RISCVExtensionBitmask<0, 27>; def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, AssemblerPredicate<(all_of FeatureStdExtZba), "'Zba' (Address Generation Instructions)">; @@ -453,7 +477,8 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; def FeatureStdExtZbb : RISCVExtension<"zbb", 1, 0, - "'Zbb' (Basic Bit-Manipulation)">; + "'Zbb' (Basic Bit-Manipulation)">, + RISCVExtensionBitmask<0, 28>; def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, AssemblerPredicate<(all_of FeatureStdExtZbb), "'Zbb' (Basic Bit-Manipulation)">; @@ -462,14 +487,16 @@ def NoStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">, def FeatureStdExtZbc : RISCVExtension<"zbc", 1, 0, - "'Zbc' (Carry-Less Multiplication)">; + "'Zbc' (Carry-Less Multiplication)">, + RISCVExtensionBitmask<0, 29>; def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, AssemblerPredicate<(all_of FeatureStdExtZbc), "'Zbc' (Carry-Less Multiplication)">; def FeatureStdExtZbs : RISCVExtension<"zbs", 1, 0, - "'Zbs' (Single-Bit Instructions)">; + "'Zbs' (Single-Bit Instructions)">, + RISCVExtensionBitmask<0, 33>; def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, AssemblerPredicate<(all_of FeatureStdExtZbs), "'Zbs' (Single-Bit Instructions)">; @@ -486,14 +513,16 @@ def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, def FeatureStdExtZbkb : RISCVExtension<"zbkb", 1, 0, - "'Zbkb' (Bitmanip instructions for Cryptography)">; + "'Zbkb' (Bitmanip instructions for Cryptography)">, + RISCVExtensionBitmask<0, 30>; def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, AssemblerPredicate<(all_of FeatureStdExtZbkb), "'Zbkb' (Bitmanip instructions for Cryptography)">; def FeatureStdExtZbkx : RISCVExtension<"zbkx", 1, 0, - "'Zbkx' (Crossbar permutation instructions)">; + "'Zbkx' (Crossbar permutation instructions)">, + RISCVExtensionBitmask<0, 32>; def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, AssemblerPredicate<(all_of FeatureStdExtZbkx), "'Zbkx' (Crossbar permutation instructions)">; @@ -510,7 +539,8 @@ def HasStdExtZbbOrZbkb def FeatureStdExtZbkc : RISCVExtension<"zbkc", 1, 0, "'Zbkc' (Carry-less multiply instructions for " - "Cryptography)">; + "Cryptography)">, + RISCVExtensionBitmask<0, 31>; def HasStdExtZbkc : Predicate<"Subtarget->hasStdExtZbkc()">, AssemblerPredicate<(all_of FeatureStdExtZbkc), @@ -527,14 +557,16 @@ def HasStdExtZbcOrZbkc def FeatureStdExtZknd : RISCVExtension<"zknd", 1, 0, - "'Zknd' (NIST Suite: AES Decryption)">; + "'Zknd' (NIST Suite: AES Decryption)">, + RISCVExtensionBitmask<0, 41>; def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, AssemblerPredicate<(all_of FeatureStdExtZknd), "'Zknd' (NIST Suite: AES Decryption)">; def FeatureStdExtZkne : RISCVExtension<"zkne", 1, 0, - "'Zkne' (NIST Suite: AES Encryption)">; + "'Zkne' (NIST Suite: AES Encryption)">, + RISCVExtensionBitmask<0, 42>; def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, AssemblerPredicate<(all_of FeatureStdExtZkne), "'Zkne' (NIST Suite: AES Encryption)">; @@ -549,21 +581,24 @@ def HasStdExtZkndOrZkne def FeatureStdExtZknh : RISCVExtension<"zknh", 1, 0, - "'Zknh' (NIST Suite: Hash Function Instructions)">; + "'Zknh' (NIST Suite: Hash Function Instructions)">, + RISCVExtensionBitmask<0, 43>; def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, AssemblerPredicate<(all_of FeatureStdExtZknh), "'Zknh' (NIST Suite: Hash Function Instructions)">; def FeatureStdExtZksed : RISCVExtension<"zksed", 1, 0, - "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; + "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">, + RISCVExtensionBitmask<0, 44>; def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, AssemblerPredicate<(all_of FeatureStdExtZksed), "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; def FeatureStdExtZksh : RISCVExtension<"zksh", 1, 0, - "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; + "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">, + RISCVExtensionBitmask<0, 45>; def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, AssemblerPredicate<(all_of FeatureStdExtZksh), "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; @@ -596,7 +631,8 @@ def FeatureStdExtZks def FeatureStdExtZkt : RISCVExtension<"zkt", 1, 0, - "'Zkt' (Data Independent Execution Latency)">; + "'Zkt' (Data Independent Execution Latency)">, + RISCVExtensionBitmask<0, 46>; def FeatureStdExtZk : RISCVExtension<"zk", 1, 0, @@ -626,6 +662,7 @@ def FeatureStdExtZve32x "with maximal 32 EEW)", [FeatureStdExtZicsr, FeatureStdExtZvl32b]>; + def FeatureStdExtZve32f : RISCVExtension<"zve32f", 1, 0, "'Zve32f' (Vector Extensions for Embedded Processors " @@ -653,7 +690,8 @@ def FeatureStdExtZve64d def FeatureStdExtV : RISCVExtension<"v", 1, 0, "'V' (Vector Extension for Application Processors)", - [FeatureStdExtZvl128b, FeatureStdExtZve64d]>; + [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, + RISCVExtensionBitmask<0, 21>; def FeatureStdExtZvfbfmin : RISCVExtension<"zvfbfmin", 1, 0, "'Zvbfmin' (Vector BF16 Converts)", @@ -673,12 +711,14 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, def FeatureStdExtZvfhmin : RISCVExtension<"zvfhmin", 1, 0, "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", - [FeatureStdExtZve32f]>; + [FeatureStdExtZve32f]>, + RISCVExtensionBitmask<0, 51>; def FeatureStdExtZvfh : RISCVExtension<"zvfh", 1, 0, "'Zvfh' (Vector Half-Precision Floating-Point)", - [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>; + [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>, + RISCVExtensionBitmask<0, 50>; def HasStdExtZfhOrZvfh : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">, @@ -690,7 +730,8 @@ def HasStdExtZfhOrZvfh def FeatureStdExtZvkb : RISCVExtension<"zvkb", 1, 0, - "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; + "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, + RISCVExtensionBitmask<0, 52>; def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, AssemblerPredicate<(all_of FeatureStdExtZvkb), "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; @@ -698,35 +739,40 @@ def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, def FeatureStdExtZvbb : RISCVExtension<"zvbb", 1, 0, "'Zvbb' (Vector basic bit-manipulation instructions)", - [FeatureStdExtZvkb]>; + [FeatureStdExtZvkb]>, + RISCVExtensionBitmask<0, 48>; def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, AssemblerPredicate<(all_of FeatureStdExtZvbb), "'Zvbb' (Vector basic bit-manipulation instructions)">; def FeatureStdExtZvbc : RISCVExtension<"zvbc", 1, 0, - "'Zvbc' (Vector Carryless Multiplication)">; + "'Zvbc' (Vector Carryless Multiplication)">, + RISCVExtensionBitmask<0, 49>; def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; def FeatureStdExtZvkg : RISCVExtension<"zvkg", 1, 0, - "'Zvkg' (Vector GCM instructions for Cryptography)">; + "'Zvkg' (Vector GCM instructions for Cryptography)">, + RISCVExtensionBitmask<0, 53>; def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, AssemblerPredicate<(all_of FeatureStdExtZvkg), "'Zvkg' (Vector GCM instructions for Cryptography)">; def FeatureStdExtZvkned : RISCVExtension<"zvkned", 1, 0, - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, + RISCVExtensionBitmask<0, 54>; def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, AssemblerPredicate<(all_of FeatureStdExtZvkned), "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; def FeatureStdExtZvknha : RISCVExtension<"zvknha", 1, 0, - "'Zvknha' (Vector SHA-2 (SHA-256 only))">; + "'Zvknha' (Vector SHA-2 (SHA-256 only))">, + RISCVExtensionBitmask<0, 55>; def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, AssemblerPredicate<(all_of FeatureStdExtZvknha), "'Zvknha' (Vector SHA-2 (SHA-256 only))">; @@ -734,7 +780,8 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, def FeatureStdExtZvknhb : RISCVExtension<"zvknhb", 1, 0, "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", - [FeatureStdExtZve64x]>; + [FeatureStdExtZve64x]>, + RISCVExtensionBitmask<0, 56>; def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, AssemblerPredicate<(all_of FeatureStdExtZvknhb), "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; @@ -745,21 +792,24 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg def FeatureStdExtZvksed : RISCVExtension<"zvksed", 1, 0, - "'Zvksed' (SM4 Block Cipher Instructions)">; + "'Zvksed' (SM4 Block Cipher Instructions)">, + RISCVExtensionBitmask<0, 57>; def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, AssemblerPredicate<(all_of FeatureStdExtZvksed), "'Zvksed' (SM4 Block Cipher Instructions)">; def FeatureStdExtZvksh : RISCVExtension<"zvksh", 1, 0, - "'Zvksh' (SM3 Hash Function Instructions)">; + "'Zvksh' (SM3 Hash Function Instructions)">, + RISCVExtensionBitmask<0, 58>; def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, AssemblerPredicate<(all_of FeatureStdExtZvksh), "'Zvksh' (SM3 Hash Function Instructions)">; def FeatureStdExtZvkt : RISCVExtension<"zvkt", 1, 0, - "'Zvkt' (Vector Data-Independent Execution Latency)">; + "'Zvkt' (Vector Data-Independent Execution Latency)">, + RISCVExtensionBitmask<0, 59>; // Zvk short-hand extensions @@ -796,7 +846,6 @@ def FeatureStdExtZvksg : RISCVExtension<"zvksg", 1, 0, "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')", [FeatureStdExtZvks, FeatureStdExtZvkg]>; - // Vector instruction predicates def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index 9003f9beffa7e..adb594777be80 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -119,6 +119,38 @@ void getFeaturesForCPU(StringRef CPU, else EnabledFeatures.push_back(F.substr(1)); } + +namespace RISCVExtensionBitmaskTable { +#define GET_RISCVExtensionBitmaskTable_IMPL +#include "llvm/TargetParser/RISCVTargetParserDef.inc" + +} // namespace RISCVExtensionBitmaskTable + +namespace { +struct LessExtName { + bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS, + StringRef RHS) { + return StringRef(LHS.Name) < RHS; + } + bool + operator()(StringRef LHS, + const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &RHS) { + return LHS < StringRef(RHS.Name); + } +}; +} // namespace + +static RISCVExtensionBitmaskTable::RISCVExtensionBitmask +getExtensionBitmask(StringRef ExtName) { + ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks = + RISCVExtensionBitmaskTable::ExtensionBitmask; + auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName()); + + if (I != ExtBitmasks.end()) + return *I; + + return RISCVExtensionBitmaskTable::RISCVExtensionBitmask(); +} } // namespace RISCV namespace RISCVVType { diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index fb58448d7ce88..9e027d18b76fb 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -12,6 +12,11 @@ class RISCVExtension<string name, int major, int minor, string desc, bit Experimental = false; } +class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> { + int GroupID = groupID; + int BitPos = bitmaskShift; +} + class RISCVExperimentalExtension<string name, int major, int minor, string desc, list<RISCVExtension> implies = [], string fieldname = !subst("Feature", "Has", NAME), @@ -23,7 +28,8 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc, def FeatureStdExtI : RISCVExtension<"i", 2, 1, - "'I' (Base Integer Instruction Set)">; + "'I' (Base Integer Instruction Set)">, + RISCVExtensionBitmask<0, 8>; def FeatureStdExtZicsr : RISCVExtension<"zicsr", 2, 0, @@ -36,7 +42,8 @@ def FeatureStdExtZifencei def FeatureStdExtF : RISCVExtension<"f", 2, 2, "'F' (Single-Precision Floating-Point)", - [FeatureStdExtZicsr]>; + [FeatureStdExtZicsr]>, + RISCVExtensionBitmask<0, 5>; def FeatureStdExtZidummy : RISCVExperimentalExtension<"zidummy", 0, 1, @@ -171,3 +178,10 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK-NEXT: TUNE_PROC(ROCKET, "rocket") // CHECK: #undef TUNE_PROC + +// CHECK: #ifdef GET_RISCVExtensionBitmaskTable_IMPL +// CHECK-NEXT: static const RISCVExtensionBitmask ExtensionBitmask[]={ +// CHECK-NEXT: {"f", 0, 5ULL}, +// CHECK-NEXT: {"i", 0, 8ULL}, +// CHECK-NEXT: }; +// CHECK-NEXT: #endif diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index b76ba05954aa5..edb1a4d5d8531 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/DenseSet.h" #include "llvm/Support/RISCVISAUtils.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" @@ -210,10 +211,46 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { OS << "\n#undef TUNE_PROC\n"; } +static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) { + + std::vector<Record *> Extensions = + RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask"); + llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) { + return getExtensionName(Rec1) < getExtensionName(Rec2); + }); + +#ifndef NDEBUG + llvm::DenseSet<std::pair<uint64_t, uint64_t>> Seen; +#endif + + OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n"; + OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n"; + for (const Record *Rec : Extensions) { + unsigned GroupIDVal = Rec->getValueAsInt("GroupID"); + unsigned BitPosVal = Rec->getValueAsInt("BitPos"); + + StringRef ExtName = Rec->getValueAsString("Name"); + ExtName.consume_front("experimental-"); + +#ifndef NDEBUG + assert(Seen.insert(std::make_pair(GroupIDVal, BitPosVal)).second && + "duplicated bitmask"); +#endif + + OS << " {" + << "\"" << ExtName << "\"" + << ", " << GroupIDVal << ", " << BitPosVal << "ULL" + << "},\n"; + } + OS << "};\n"; + OS << "#endif\n"; +} + static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) { emitRISCVExtensions(RK, OS); emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); + emitRISCVExtensionBitmask(RK, OS); } static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef, >From 205f27e3261a3ba30b608e399f93ab6e8c03b3dd Mon Sep 17 00:00:00 2001 From: Piyou Chen <piyou.c...@sifive.com> Date: Thu, 11 Jul 2024 20:48:02 -0700 Subject: [PATCH 2/6] Add zihintpause --- llvm/lib/Target/RISCV/RISCVFeatures.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 125e9e2f53953..ff6ec42a2e72f 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -139,7 +139,8 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, def FeatureStdExtZihintpause : RISCVExtension<"zihintpause", 2, 0, - "'Zihintpause' (Pause Hint)">; + "'Zihintpause' (Pause Hint)">, + RISCVExtensionBitmask<0, 40>; def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, AssemblerPredicate<(all_of FeatureStdExtZihintpause), "'Zihintpause' (Pause Hint)">; >From 0a873d0897fbbf94d46e6fbf129aee3090b4b9c1 Mon Sep 17 00:00:00 2001 From: Piyou Chen <piyou.c...@sifive.com> Date: Mon, 10 Jun 2024 22:22:42 -0700 Subject: [PATCH 3/6] [RISCV][FMV] Support target_clones --- .../clang/Basic/DiagnosticFrontendKinds.td | 4 + clang/include/clang/Basic/TargetInfo.h | 3 +- clang/lib/AST/ASTContext.cpp | 12 + clang/lib/CodeGen/CGBuiltin.cpp | 78 +++++++ clang/lib/CodeGen/CodeGenFunction.cpp | 91 +++++++- clang/lib/CodeGen/CodeGenFunction.h | 7 + clang/lib/CodeGen/CodeGenModule.cpp | 5 +- clang/lib/CodeGen/Targets/RISCV.cpp | 23 ++ clang/lib/Sema/SemaDeclAttr.cpp | 26 +++ .../attr-target-clones-riscv-invaild.c | 8 + clang/test/CodeGen/attr-target-clones-riscv.c | 205 ++++++++++++++++++ .../CodeGenCXX/attr-target-clones-riscv.cpp | 204 +++++++++++++++++ .../test/SemaCXX/attr-target-clones-riscv.cpp | 32 +++ .../llvm/TargetParser/RISCVTargetParser.h | 4 + llvm/lib/TargetParser/RISCVTargetParser.cpp | 18 +- 15 files changed, 715 insertions(+), 5 deletions(-) create mode 100644 clang/test/CodeGen/attr-target-clones-riscv-invaild.c create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td b/clang/include/clang/Basic/DiagnosticFrontendKinds.td index 12a4617c64d87..b2b63674ecc07 100644 --- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td +++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td @@ -375,4 +375,8 @@ def warn_missing_symbol_graph_dir : Warning< def err_ast_action_on_llvm_ir : Error< "cannot apply AST actions to LLVM IR file '%0'">, DefaultFatal; + +def err_os_unsupport_riscv_target_clones : Error< + "target_clones is currently only supported on Linux">; + } diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index cf7628553647c..40fbc3a1116cb 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1519,7 +1519,8 @@ class TargetInfo : public TransferrableTargetInfo, /// Identify whether this target supports multiversioning of functions, /// which requires support for cpu_supports and cpu_is functionality. bool supportsMultiVersioning() const { - return getTriple().isX86() || getTriple().isAArch64(); + return getTriple().isX86() || getTriple().isAArch64() || + getTriple().isRISCV(); } /// Identify whether this target supports IFuncs. diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 8e35e71d4a23e..29dce55f349ec 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -13839,6 +13839,18 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap, Target->getTargetOpts().FeaturesAsWritten.begin(), Target->getTargetOpts().FeaturesAsWritten.end()); Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features); + } else if (Target->getTriple().isRISCV()) { + StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex()); + std::vector<std::string> Features; + if (VersionStr != "default") { + ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr); + Features.insert(Features.begin(), ParsedAttr.Features.begin(), + ParsedAttr.Features.end()); + } + Features.insert(Features.begin(), + Target->getTargetOpts().FeaturesAsWritten.begin(), + Target->getTargetOpts().FeaturesAsWritten.end()); + Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features); } else { std::vector<std::string> Features; StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex()); diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 6cc0d9485720c..42647224a88a4 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -62,6 +62,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/TargetParser/AArch64TargetParser.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/TargetParser/X86TargetParser.h" #include <optional> #include <sstream> @@ -14214,6 +14215,16 @@ Value *CodeGenFunction::EmitAArch64CpuInit() { return Builder.CreateCall(Func); } +Value *CodeGenFunction::EmitRISCVCpuInit() { + llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false); + llvm::FunctionCallee Func = + CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bit"); + cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true); + cast<llvm::GlobalValue>(Func.getCallee()) + ->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass); + return Builder.CreateCall(Func); +} + Value *CodeGenFunction::EmitX86CpuInit() { llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, /*Variadic*/ false); @@ -14266,6 +14277,73 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef<StringRef> FeaturesStrs) { return Result; } +Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs, + unsigned &MaxGroupIDUsed) { + + const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize; + llvm::ArrayType *ArrayOfInt64Ty = + llvm::ArrayType::get(Int64Ty, FeatureBitSize); + llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty); + llvm::Constant *RISCVFeaturesBits = + CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits"); + cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true); + + auto LoadFeatureBit = [&](unsigned Index) { + // Create GEP then load. + Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index); + std::vector<llvm::Value *> GEPIndices = {llvm::ConstantInt::get(Int32Ty, 0), + llvm::ConstantInt::get(Int32Ty, 1), + IndexVal}; + Value *Ptr = + Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices); + Value *FeaturesBit = + Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8)); + return FeaturesBit; + }; + + SmallVector<unsigned long long> RequireFeatureBits = + llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs); + Value *Result = Builder.getTrue(); + for (unsigned i = 0; i < RequireFeatureBits.size(); i++) { + if (!RequireFeatureBits[i]) + continue; + MaxGroupIDUsed = i; + Value *Mask = Builder.getInt64(RequireFeatureBits[i]); + Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask); + Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask); + Result = Builder.CreateAnd(Result, Cmp); + } + + return Result; +} + +Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) { + + const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize; + llvm::ArrayType *ArrayOfInt64Ty = + llvm::ArrayType::get(Int64Ty, FeatureBitSize); + llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty); + llvm::Constant *RISCVFeaturesBits = + CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits"); + cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true); + + auto LoadMaxGroupID = [&]() { + std::vector<llvm::Value *> GEPIndices = { + llvm::ConstantInt::get(Int32Ty, 0), llvm::ConstantInt::get(Int32Ty, 0)}; + llvm::Value *Ptr = + Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices); + Value *Length = + Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8)); + return Length; + }; + + Value *UsedMaxGroupID = Builder.getInt64(MaxGroupIDUsed); + Value *GroupIDResult = + Builder.CreateICmpULT(UsedMaxGroupID, LoadMaxGroupID()); + + return GroupIDResult; +} + Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, const CallExpr *E) { if (BuiltinID == Builtin::BI__builtin_cpu_is) diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index 26deeca95d326..27305e0f4b7b4 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -2854,10 +2854,99 @@ void CodeGenFunction::EmitMultiVersionResolver( case llvm::Triple::aarch64: EmitAArch64MultiVersionResolver(Resolver, Options); return; + case llvm::Triple::riscv32: + case llvm::Triple::riscv64: + EmitRISCVMultiVersionResolver(Resolver, Options); + return; default: - assert(false && "Only implemented for x86 and AArch64 targets"); + assert(false && "Only implemented for x86, AArch64 and RISC-V targets"); + } +} + +void CodeGenFunction::EmitRISCVMultiVersionResolver( + llvm::Function *Resolver, ArrayRef<MultiVersionResolverOption> Options) { + + if (getContext().getTargetInfo().getTriple().getOS() != + llvm::Triple::OSType::Linux) { + CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones); + return; + } + + llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver); + Builder.SetInsertPoint(CurBlock); + EmitRISCVCpuInit(); + + bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc(); + bool HasDefault = false; + int DefaultIndex = 0; + // Check the each candidate function. + for (unsigned Index = 0; Index < Options.size(); Index++) { + + if (Options[Index].Conditions.Features[0].starts_with("default")) { + HasDefault = true; + DefaultIndex = Index; + continue; + } + + Builder.SetInsertPoint(CurBlock); + + std::vector<std::string> TargetAttrFeats = + getContext() + .getTargetInfo() + .parseTargetAttr(Options[Index].Conditions.Features[0]) + .Features; + + if (!TargetAttrFeats.empty()) { + + llvm::BasicBlock *SecondCond = + createBasicBlock("resovler_cond", Resolver); + + Builder.SetInsertPoint(SecondCond); + unsigned MaxGroupIDUsed = 0; + llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats; + + for (auto Feat: TargetAttrFeats) + CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1)); + + llvm::Value *SecondCondition = + EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed); + + Builder.SetInsertPoint(CurBlock); + llvm::Value *FirstCondition = EmitRISCVFeatureBitsLength(MaxGroupIDUsed); + + llvm::BasicBlock *RetBlock = + createBasicBlock("resolver_return", Resolver); + CGBuilderTy RetBuilder(*this, RetBlock); + CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder, + Options[Index].Function, SupportsIFunc); + llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver); + + Builder.SetInsertPoint(CurBlock); + Builder.CreateCondBr(FirstCondition, SecondCond, ElseBlock); + + Builder.SetInsertPoint(SecondCond); + Builder.CreateCondBr(SecondCondition, RetBlock, ElseBlock); + + CurBlock = ElseBlock; + } } + + // Finally, emit the default one. + if (HasDefault) { + Builder.SetInsertPoint(CurBlock); + CreateMultiVersionResolverReturn( + CGM, Resolver, Builder, Options[DefaultIndex].Function, SupportsIFunc); + return; + } + + // If no generic/default, emit an unreachable. + Builder.SetInsertPoint(CurBlock); + llvm::CallInst *TrapCall = EmitTrapCall(llvm::Intrinsic::trap); + TrapCall->setDoesNotReturn(); + TrapCall->setDoesNotThrow(); + Builder.CreateUnreachable(); + Builder.ClearInsertionPoint(); } void CodeGenFunction::EmitAArch64MultiVersionResolver( diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 13f12b5d878a6..107701d3f1faa 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -5291,6 +5291,9 @@ class CodeGenFunction : public CodeGenTypeCache { void EmitAArch64MultiVersionResolver(llvm::Function *Resolver, ArrayRef<MultiVersionResolverOption> Options); + void + EmitRISCVMultiVersionResolver(llvm::Function *Resolver, + ArrayRef<MultiVersionResolverOption> Options); private: QualType getVarArgType(const Expr *Arg); @@ -5315,6 +5318,10 @@ class CodeGenFunction : public CodeGenTypeCache { FormAArch64ResolverCondition(const MultiVersionResolverOption &RO); llvm::Value *EmitAArch64CpuSupports(const CallExpr *E); llvm::Value *EmitAArch64CpuSupports(ArrayRef<StringRef> FeatureStrs); + llvm::Value *EmitRISCVCpuInit(); + llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeatureStrs, + unsigned &MaxGroupIDUsed); + llvm::Value *EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed); }; inline DominatingLLVMValue::saved_type diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 5c810cd332185..d876dff3d5755 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -4257,7 +4257,10 @@ void CodeGenModule::emitMultiVersionFunctions() { Feats.clear(); if (getTarget().getTriple().isAArch64()) TC->getFeatures(Feats, I); - else { + else if (getTarget().getTriple().isRISCV()) { + StringRef Version = TC->getFeatureStr(I); + Feats.push_back(Version); + } else { StringRef Version = TC->getFeatureStr(I); if (Version.starts_with("arch=")) Architecture = Version.drop_front(sizeof("arch=") - 1); diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp index f2add9351c03c..ba81bf7d1dd0a 100644 --- a/clang/lib/CodeGen/Targets/RISCV.cpp +++ b/clang/lib/CodeGen/Targets/RISCV.cpp @@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo { CharUnits Field2Off) const; ABIArgInfo coerceVLSVector(QualType Ty) const; + + using ABIInfo::appendAttributeMangling; + void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index, + raw_ostream &Out) const override; + void appendAttributeMangling(StringRef AttrStr, + raw_ostream &Out) const override; }; } // end anonymous namespace +void RISCVABIInfo::appendAttributeMangling(TargetClonesAttr *Attr, + unsigned Index, + raw_ostream &Out) const { + appendAttributeMangling(Attr->getFeatureStr(Index), Out); +} + +void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr, + raw_ostream &Out) const { + if (AttrStr == "default") { + Out << ".default"; + return; + } + + Out << '.'; + Out << AttrStr; +} + void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { QualType RetTy = FI.getReturnType(); if (!getCXXABI().classifyReturnType(FI)) diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index f2cd46d1e7c93..9b420f90b222f 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -3127,6 +3127,32 @@ bool Sema::checkTargetClonesAttrString( /*IncludeLocallyStreaming=*/false)) return Diag(LiteralLoc, diag::err_sme_streaming_cannot_be_multiversioned); + } else if (TInfo.getTriple().isRISCV()) { + // Suppress warn_target_clone_mixed_values + HasCommas = false; + + // Only support arch=+ext,... syntax. + if (Str.starts_with("arch=+")) { + // parseTargetAttr will parse full version string, + // the following split Cur string is no longer interesting. + if ((!Cur.starts_with("arch="))) + continue; + + ParsedTargetAttr TargetAttr = + Context.getTargetInfo().parseTargetAttr(Str); + if (TargetAttr.Features.empty()) + return Diag(CurLoc, diag::warn_unsupported_target_attribute) + << Unsupported << None << Str << TargetClones; + } else if (Str == "default") { + DefaultIsDupe = HasDefault; + HasDefault = true; + } else { + return Diag(CurLoc, diag::warn_unsupported_target_attribute) + << Unsupported << None << Str << TargetClones; + } + if (llvm::is_contained(StringsBuffer, Str) || DefaultIsDupe) + Diag(CurLoc, diag::warn_target_clone_duplicate_options); + StringsBuffer.push_back(Str); } else { // Other targets ( currently X86 ) if (Cur.starts_with("arch=")) { diff --git a/clang/test/CodeGen/attr-target-clones-riscv-invaild.c b/clang/test/CodeGen/attr-target-clones-riscv-invaild.c new file mode 100644 index 0000000000000..f5e8f40d7a8f3 --- /dev/null +++ b/clang/test/CodeGen/attr-target-clones-riscv-invaild.c @@ -0,0 +1,8 @@ +// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS + +// CHECK-UNSUPPORT-OS: error: target_clones is currently only supported on Linux +__attribute__((target_clones("default", "arch=+c"))) int foo2(void) { + return 2; +} + +int bar() { return foo1()+foo2(); } diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c new file mode 100644 index 0000000000000..1088dd56a4d83 --- /dev/null +++ b/clang/test/CodeGen/attr-target-clones-riscv.c @@ -0,0 +1,205 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4 +// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o - %s | FileCheck %s + +__attribute__((target_clones("default", "arch=+m"))) int foo1(void) { + return 1; +} +__attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; } +__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; } +__attribute__((target_clones("default", "arch=+zbb,+v"))) int +foo4(void) { + return 4; +} +__attribute__((target_clones("default"))) int foo5(void) { return 5; } +__attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; } + +int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } + +//. +// CHECK: @__riscv_feature_bits = external dso_local global { i32, [1 x i64] } +// CHECK: @foo1.ifunc = weak_odr alias i32 (), ptr @foo1 +// CHECK: @foo2.ifunc = weak_odr alias i32 (), ptr @foo2 +// CHECK: @foo3.ifunc = weak_odr alias i32 (), ptr @foo3 +// CHECK: @foo4.ifunc = weak_odr alias i32 (), ptr @foo4 +// CHECK: @foo5.ifunc = weak_odr alias i32 (), ptr @foo5 +// CHECK: @foo6.ifunc = weak_odr alias i32 (), ptr @foo6 +// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver +// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver +// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver +// CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver +// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver +// CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver +//. +// CHECK-LABEL: define dso_local signext i32 @foo1.default( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"foo1.arch=+m" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @foo1.default +// +// +// CHECK-LABEL: define dso_local signext i32 @foo2.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 2 +// +// +// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"foo2.arch=+zbb" +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 0, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOVLER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]] +// CHECK: resovler_cond1: +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096 +// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096 +// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] +// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]] +// CHECK: resolver_return2: +// CHECK-NEXT: ret ptr @"foo2.arch=+m" +// CHECK: resolver_else3: +// CHECK-NEXT: ret ptr @foo2.default +// +// +// CHECK-LABEL: define dso_local signext i32 @foo3.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 3 +// +// +// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"foo3.arch=+zbb,+c" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @foo3.default +// +// +// CHECK-LABEL: define dso_local signext i32 @foo4.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 4 +// +// +// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"foo4.arch=+zbb,+v" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @foo4.default +// +// +// CHECK-LABEL: define dso_local signext i32 @foo5.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 5 +// +// +// CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: ret ptr @foo5.default +// +// +// CHECK-LABEL: define dso_local signext i32 @foo6.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 2 +// +// +// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"foo6.arch=+zvkt" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @foo6.default +// +// +// CHECK-LABEL: define dso_local signext i32 @bar( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1() +// CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2() +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] +// CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3() +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] +// CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4() +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] +// CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5() +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] +// CHECK-NEXT: ret i32 [[ADD7]] +// +//. +// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } +// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" } +// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" } +// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb" } +// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zbb,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } +// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zvkt" } +//. +// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"} +// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]} +// CHECK: [[META3]] = !{!"rv64i2p1"} +// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0} +// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp new file mode 100644 index 0000000000000..73bbfcd8b9652 --- /dev/null +++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp @@ -0,0 +1,204 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4 +// RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s + +__attribute__((target_clones("default", "arch=+m"))) int foo1(void) { + return 1; +} +__attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; } +__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; } +__attribute__((target_clones("default", "arch=+zbb,+v"))) int +foo4(void) { + return 4; +} +__attribute__((target_clones("default"))) int foo5(void) { return 5; } +__attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; } + +int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } + +//. +// CHECK: @__riscv_feature_bits = external dso_local global { i32, [1 x i64] } +// CHECK: @_Z4foo1v.ifunc = weak_odr alias i32 (), ptr @_Z4foo1v +// CHECK: @_Z4foo2v.ifunc = weak_odr alias i32 (), ptr @_Z4foo2v +// CHECK: @_Z4foo3v.ifunc = weak_odr alias i32 (), ptr @_Z4foo3v +// CHECK: @_Z4foo4v.ifunc = weak_odr alias i32 (), ptr @_Z4foo4v +// CHECK: @_Z4foo5v.ifunc = weak_odr alias i32 (), ptr @_Z4foo5v +// CHECK: @_Z4foo6v.ifunc = weak_odr alias i32 (), ptr @_Z4foo6v +// CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver +// CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver +// CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver +// CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver +// CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver +// CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver +//. +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"_Z4foo1v.arch=+m" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @_Z4foo1v.default +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 2 +// +// +// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+zbb" +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 0, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOVLER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]] +// CHECK: resovler_cond1: +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096 +// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096 +// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] +// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]] +// CHECK: resolver_return2: +// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+m" +// CHECK: resolver_else3: +// CHECK-NEXT: ret ptr @_Z4foo2v.default +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 3 +// +// +// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"_Z4foo3v.arch=+zbb,+c" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @_Z4foo3v.default +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 4 +// +// +// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"_Z4foo4v.arch=+zbb,+v" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @_Z4foo4v.default +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 5 +// +// +// CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: ret ptr @_Z4foo5v.default +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 2 +// +// +// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] +// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resovler_cond: +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 +// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488 +// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488 +// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]] +// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @"_Z4foo6v.arch=+zvkt" +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @_Z4foo6v.default +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv( +// CHECK-SAME: ) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v() +// CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v() +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] +// CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v() +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] +// CHECK-NEXT: [[CALL4:%.*]] = call noundef signext i32 @_Z4foo4v() +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] +// CHECK-NEXT: [[CALL6:%.*]] = call noundef signext i32 @_Z4foo5v() +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] +// CHECK-NEXT: ret i32 [[ADD7]] +// +//. +// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" } +// CHECK: attributes #[[ATTR1:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" } +// CHECK: attributes #[[ATTR2:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" } +// CHECK: attributes #[[ATTR3:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } +// CHECK: attributes #[[ATTR4:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" } +//. +// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"} +// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]} +// CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"} +// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0} +// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/SemaCXX/attr-target-clones-riscv.cpp b/clang/test/SemaCXX/attr-target-clones-riscv.cpp new file mode 100644 index 0000000000000..edee5f7c231e9 --- /dev/null +++ b/clang/test/SemaCXX/attr-target-clones-riscv.cpp @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 -triple riscv64-linux-gnu -fsyntax-only -verify -fexceptions -fcxx-exceptions %s -std=c++14 + +// expected-warning@+1 {{unsupported 'mcpu=sifive-u74' in the 'target_clones' attribute string; 'target_clones' attribute ignored}} +void __attribute__((target_clones("default", "mcpu=sifive-u74"))) mcpu() {} + +// expected-warning@+1 {{unsupported 'mtune=sifive-u74' in the 'target_clones' attribute string; 'target_clones' attribute ignored}} +void __attribute__((target_clones("default", "mtune=sifive-u74"))) mtune() {} + +// expected-warning@+1 {{version list contains duplicate entries}} +void __attribute__((target_clones("default", "arch=+c", "arch=+c"))) dupVersion() {} + +// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string; 'target_clones' attribute ignored}} +void __attribute__((target_clones("default", ""))) emptyVersion() {} + +// expected-error@+1 {{'target_clones' multiversioning requires a default target}} +void __attribute__((target_clones("arch=+c"))) withoutDefault() {} + +// expected-warning@+1 {{unsupported '+c' in the 'target_clones' attribute string; 'target_clones' attribute ignored}} +void __attribute__((target_clones("default", "+c"))) invaildVersion() {} + +// expected-warning@+1 {{unsupported 'arch=rv64g' in the 'target_clones' attribute string; 'target_clones' attribute ignored}} +void __attribute__((target_clones("default", "arch=rv64g"))) fullArchString() {} + + +void lambda() { + // expected-error@+1 {{attribute 'target_clones' multiversioned functions do not yet support lambdas}} + auto x = []() __attribute__((target_clones("default"))){}; + x(); + // expected-error@+1 {{attribute 'target_clones' multiversioned functions do not yet support lambdas}} + auto y = []() __attribute__((target_clones("arch=+v", "default"))){}; + y(); +} diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index e998bc4ca59ee..59f4bc6c80f97 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -32,6 +32,8 @@ struct RISCVExtensionBitmask { }; } // namespace RISCVExtensionBitmaskTable +static constexpr unsigned RISCVFeatureBitSize = 1; + // We use 64 bits as the known part in the scalable vector types. static constexpr unsigned RVVBitsPerBlock = 64; @@ -44,6 +46,8 @@ StringRef getMArchFromMcpu(StringRef CPU); void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); bool hasFastUnalignedAccess(StringRef CPU); +llvm::SmallVector<unsigned long long> + getRequireFeatureBitMask(ArrayRef<StringRef>); } // namespace RISCV diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index adb594777be80..2f9fef594e894 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -140,7 +140,7 @@ struct LessExtName { }; } // namespace -static RISCVExtensionBitmaskTable::RISCVExtensionBitmask +static Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> getExtensionBitmask(StringRef ExtName) { ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks = RISCVExtensionBitmaskTable::ExtensionBitmask; @@ -149,7 +149,21 @@ getExtensionBitmask(StringRef ExtName) { if (I != ExtBitmasks.end()) return *I; - return RISCVExtensionBitmaskTable::RISCVExtensionBitmask(); + return createStringError("Unsupport extension"); +} + +llvm::SmallVector<unsigned long long> +getRequireFeatureBitMask(ArrayRef<StringRef> Exts) { + llvm::SmallVector<unsigned long long> BitMasks(RISCV::RISCVFeatureBitSize); + + for (auto Ext : Exts) { + Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmask = + getExtensionBitmask(Ext); + assert(ExtBitmask && "This extension doesn't has bitmask."); + BitMasks[ExtBitmask->GroupID] |= (1ULL << ExtBitmask->BitPosition); + } + + return BitMasks; } } // namespace RISCV >From 10f8f50f67a381153f8a1b49834cfcf93a94dcd1 Mon Sep 17 00:00:00 2001 From: Piyou Chen <piyou.c...@sifive.com> Date: Fri, 12 Jul 2024 02:17:34 -0700 Subject: [PATCH 4/6] Fixup format --- clang/lib/CodeGen/CodeGenFunction.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index 27305e0f4b7b4..f2b2915878a90 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -2906,9 +2906,9 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver( unsigned MaxGroupIDUsed = 0; llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats; - for (auto Feat: TargetAttrFeats) + for (auto Feat : TargetAttrFeats) CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1)); - + llvm::Value *SecondCondition = EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed); >From 85264d19c988144745df77c9578a6c96287be0e4 Mon Sep 17 00:00:00 2001 From: Piyou Chen <piyou.c...@sifive.com> Date: Tue, 16 Jul 2024 06:15:27 -0700 Subject: [PATCH 5/6] __init_riscv_features_bit -> __init_riscv_features_bits --- clang/lib/CodeGen/CGBuiltin.cpp | 2 +- clang/test/CodeGen/attr-target-clones-riscv.c | 12 ++++++------ clang/test/CodeGenCXX/attr-target-clones-riscv.cpp | 12 ++++++------ 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 42647224a88a4..83ad64cb1cc3c 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -14218,7 +14218,7 @@ Value *CodeGenFunction::EmitAArch64CpuInit() { Value *CodeGenFunction::EmitRISCVCpuInit() { llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false); llvm::FunctionCallee Func = - CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bit"); + CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bits"); cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true); cast<llvm::GlobalValue>(Func.getCallee()) ->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass); diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c index 1088dd56a4d83..38adba7eac312 100644 --- a/clang/test/CodeGen/attr-target-clones-riscv.c +++ b/clang/test/CodeGen/attr-target-clones-riscv.c @@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: ret ptr @foo5.default // // @@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp index 73bbfcd8b9652..024c1c715c617 100644 --- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp +++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp @@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: ret ptr @_Z4foo5v.default // // @@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bit() +// CHECK-NEXT: call void @__init_riscv_features_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] >From 265973a60ec446f2b0f2ce292f6f045a1744dd6c Mon Sep 17 00:00:00 2001 From: Piyou Chen <piyou.c...@sifive.com> Date: Tue, 16 Jul 2024 19:06:17 -0700 Subject: [PATCH 6/6] Update __init_riscv_feature_bits naming --- clang/lib/CodeGen/CGBuiltin.cpp | 2 +- clang/test/CodeGen/attr-target-clones-riscv.c | 12 ++++++------ clang/test/CodeGenCXX/attr-target-clones-riscv.cpp | 12 ++++++------ 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 83ad64cb1cc3c..aebd826c8077f 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -14218,7 +14218,7 @@ Value *CodeGenFunction::EmitAArch64CpuInit() { Value *CodeGenFunction::EmitRISCVCpuInit() { llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false); llvm::FunctionCallee Func = - CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bits"); + CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits"); cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true); cast<llvm::GlobalValue>(Func.getCallee()) ->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass); diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c index 38adba7eac312..27e8d20f7ba17 100644 --- a/clang/test/CodeGen/attr-target-clones-riscv.c +++ b/clang/test/CodeGen/attr-target-clones-riscv.c @@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: ret ptr @foo5.default // // @@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp index 024c1c715c617..6bac679cf1425 100644 --- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp +++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp @@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] @@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: ret ptr @_Z4foo5v.default // // @@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); } // // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat { // CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_riscv_features_bits() +// CHECK-NEXT: call void @__init_riscv_feature_bits() // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8 // CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]] // CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]] _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
