https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/103299
From 04886f07618a283cc56d8a28aaf99e16d3897855 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Tue, 13 Aug 2024 14:39:03 +0200
Subject: [PATCH] [clang][HLSL] Add WaveIsLaneFirst() intrinsic
M
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/90278
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https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/88918
From 94d76dcdfac88d1d50fe705406c0280c33766e15 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 15 Apr 2024 17:05:40 +0200
Subject: [PATCH 1/4] [clang][SPIR-V] Always add convervence intri
@@ -3101,3 +3130,68 @@ CodeGenFunction::GenerateCapturedStmtFunction(const
CapturedStmt &S) {
return F;
}
+
+namespace {
+// Returns the first convergence entry/loop/anchor instruction found in |BB|.
+// std::nullptr otherwise.
+llvm::IntrinsicInst *getConvergenceToken(llvm
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/88918
From a8bf6fe83a1c145ef81ee30471dc51de1b5354ef Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 15 Apr 2024 17:05:40 +0200
Subject: [PATCH 1/5] [clang][SPIR-V] Always add convervence intri
Keenuts wrote:
Hi all, rebased on main, and addressed the comments.
This commits changes the register order on SPIR-V vs DXIL, which required me
to fix the mad+lerp intrinsic tests. Should be NFC, just storing the register
name in a CHECK variable.
https://github.com/llvm/llvm-project/pull/8
@@ -1586,6 +1586,12 @@ class CodeGenModule : public CodeGenTypeCache {
void AddGlobalDtor(llvm::Function *Dtor, int Priority = 65535,
bool IsDtorAttrFunc = false);
+ // Return whether structured convergence intrinsics should be generated for
+ // this
Keenuts wrote:
Thanks for the reviews. Waiting for 1 approval from MS and I'll merge
https://github.com/llvm/llvm-project/pull/88918
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https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/88918
From a8bf6fe83a1c145ef81ee30471dc51de1b5354ef Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 15 Apr 2024 17:05:40 +0200
Subject: [PATCH 1/6] [clang][SPIR-V] Always add convervence intri
@@ -1586,6 +1586,12 @@ class CodeGenModule : public CodeGenTypeCache {
void AddGlobalDtor(llvm::Function *Dtor, int Priority = 65535,
bool IsDtorAttrFunc = false);
+ // Return whether structured convergence intrinsics should be generated for
+ // this
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/88918
From 440cdfa4132a969702348c32f2810924012c5ea6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 15 Apr 2024 17:05:40 +0200
Subject: [PATCH 1/6] [clang][SPIR-V] Always add convervence intri
Keenuts wrote:
rebased on main, local tests are passing, waiting on CI to merge.
https://github.com/llvm/llvm-project/pull/88918
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@@ -18660,6 +18660,10 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
llvm::FunctionType::get(IntTy, {}, false),
"__hlsl_wave_get_lane_index",
{}, false, true));
}
+ case Builtin::BI__builtin_hlsl_wave_is_first_lane: {
+Intrinsic::ID ID = CGM.getH
Keenuts wrote:
Hello!
Looks like increasing the max depth makes the debug build stack overflow.
In release builds, `clang/test/Parser/parser_overflow.c` is fine, but in debug
builds, the stack size reaches my OS limit (8MB) and crashes.
Shall the max depth be reduced a bit?
https://github.com/l
Keenuts wrote:
```
$ ./build/bin/clang -fsyntax-only -DHUGE 2>&1
clang/test/Parser/parser_overflow.c -fbracket-depth=2048
Segmentation fault
$ ./build/bin/clang -fsyntax-only -DHUGE 2>&1
clang/test/Parser/parser_overflow.c -fbracket-depth=2045
clang/test/Parser/parser_overflow.c:11:2049: fatal
Keenuts wrote:
Thanks for looking into this.
I don't know what's causing the ""Virtual register defs don't dominate all
uses", as some cases are located in the middle of a block and doesn't seem to
be related to BB sorting (even though this is probably the cause)
```
127 bb.10.do.end8:
[...]
1
Keenuts wrote:
Ok, so I've figured out 3 issues:
1. A bug in my sorting of merge instructions. If LHS == RHS, I returned LHS <
RHS, that was wrong. Executed outside of GDB, it was very slow to show the
backtrace and crash, so tests looked like it was hanging, but it was just
crashing.
2. An e
Keenuts wrote:
> > OpLoopMerge are taking BB operands, but verifier expected register operand.
>
> Hopefully, the fix may be as simple as to change
> lib/Target/SPIRV/SPIRVInstrInfo.td line 620-621 `ID:$merge, ID:$continue`
> into `unknown:$merge, unknown:$continue` as in line 626 for OpBranch
Keenuts wrote:
Rebased on main.
Also had to apply a few changes:
- fixed valid expensive checks issues caused by this PR (irreflexible iterator)
This was because the BB order check was saying `A < A`.
- fixed codegen instability caused by the block sorting.
To satisfy both the SPIR-V spec an
@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -fincl
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/111010
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@@ -2653,6 +2653,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
+ case Intrinsic::spv_wave_read_lane_at: {
+assert(I.getNumOperands() == 4);
https://github.com/Keenuts commented:
Thanks for this! Some minor changes, otherwise looks good 😊
https://github.com/llvm/llvm-project/pull/111010
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https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/110306
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https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/112757
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https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/114273
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@@ -323,6 +327,82 @@ llvm::Type
*CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
return nullptr;
}
+llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
+ const Type *Ty) const {
+ auto
@@ -323,6 +327,83 @@ llvm::Type
*CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
return nullptr;
}
+llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
+ const Type *Ty) const {
+ auto
@@ -323,6 +327,83 @@ llvm::Type
*CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
return nullptr;
}
+llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
+ const Type *Ty) const {
+ auto
https://github.com/Keenuts closed
https://github.com/llvm/llvm-project/pull/107408
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@@ -415,6 +415,7 @@ void CGHLSLRuntime::emitEntryFunction(const FunctionDecl
*FD,
}
CallInst *CI = B.CreateCall(FunctionCallee(Fn), Args);
+ CI->setCallingConv(Fn->getCallingConv());
(void)CI;
Keenuts wrote:
nit: `(void)CI` can now be removed.
https
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/110275
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@@ -0,0 +1,1242 @@
+//===-- SPIRVStructurizer.cpp --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH
@@ -0,0 +1,1242 @@
+//===-- SPIRVStructurizer.cpp --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH
Keenuts wrote:
rebased. Will merge tomorrow morning if CI is green.
https://github.com/llvm/llvm-project/pull/107408
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@@ -0,0 +1,1242 @@
+//===-- SPIRVStructurizer.cpp --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH
Keenuts wrote:
Thanks! No worries!
Applied the few changes. And yes, there will be iterations on this. For
example, merge-exit pass is not completely finished, and other specific
scenarios. But this will be done through smaller PRs.
I also need to look into how to test this since people want me
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/115187
Draft PR to explore adding semantics & inline SPIR-V for builtins.
Current usage is
```hlsl
// RUN: %clang --driver-mode=dxc -T cs_6_6 -spirv %s -O3 -E main
[[vk::ext_builtin_input(/* NumWorkGroups */ 24)]]
ext
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+@PrivInternal = internal addrspace(10) global i32 456
+; CHE
Keenuts wrote:
Hello all!
Changed the PR to use a new AS emitted by the FE. This way there are no more
weird storage class switch.
However, this required to support a new `addrspacecast` operation from
`Function` to `Private` and the other way around.
The FE change will be in another PR (can b
Keenuts wrote:
@llvm-beanz : FYI for the added address space.
https://github.com/llvm/llvm-project/pull/116636
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From 30bdda1649c1c9480968f830c326554f76eabdb6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Thu, 28 Nov 2024 15:00:56 +0100
Subject: [PATCH] [SPIR-V] Add hlsl_private address space for SPI
@@ -59,6 +59,9 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ // Vulkan specific address spaces.
+ vulkan_private,
+
Keenuts wrote:
It breaks 1 test, but the test seems wrong anyway: test for
SPV_INTEL_function_p
@@ -59,6 +59,9 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ // Vulkan specific address spaces.
+ vulkan_private,
+
Keenuts wrote:
My understanding is we have 2 ways to convey this information from the FE to
the
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
https://github.com/Keenuts commented:
Thanks for this addition! Sorry late review,missed that
https://github.com/llvm/llvm-project/pull/115902
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https://github.com/llvm/llvm-project/pull/115902
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https://github.com/llvm/llvm-project/pull/115187
From 357f8e613e030967f6a95ccbeffe03c0f5f8c186 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Wed, 6 Nov 2024 17:48:13 +0100
Subject: [PATCH] [SPIR-V] DRAFT: ext_builtin_input/ext_builtin_ou
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/116393
Draft PR to explore adding semantics & inline SPIR-V for builtins. This PR is
an alternative to #115187 which does not requires a spec change as we keep the
variables as `static [const]`.
In addition, it tried
@@ -43,7 +43,7 @@ void neg() {
template
void tooBig() {
- __attribute__((address_space(I))) int *bounds; // expected-error {{address
space is larger than the maximum supported (8388586)}}
+ __attribute__((address_space(I))) int *bounds; // expected-error {{address
space i
@@ -204,7 +204,11 @@ addressSpaceToStorageClass(unsigned AddrSpace, const
SPIRVSubtarget &STI) {
? SPIRV::StorageClass::HostOnlyINTEL
: SPIRV::StorageClass::CrossWorkgroup;
case 7:
+return SPIRV::StorageClass::Private;
+ case 8:
return
@@ -379,6 +380,18 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<>
&B,
const ParmVarDecl &D,
llvm::Type *Ty) {
assert(D.hasAttrs() && "Entry parameter missing annotation a
Keenuts wrote:
> I'll check it today against my test suites and get back to you.
Thanks!
> I'm curious how `sortBlocks(F)` and other changes would behave when inserted
> before vs. after those optimizations applied?
I'm not sure either. I'd be tempted to say we should put the `sortBlock` aft
Keenuts wrote:
I created https://github.com/llvm/llvm-project/issues/108845 and
https://github.com/llvm/llvm-project/issues/108844 for some of the extensive
checks isues and added those to my schedule.
Thanks for the review!
https://github.com/llvm/llvm-project/pull/107408
Keenuts wrote:
@michalpaszkowski let me know when I can merge this (I see no warning on my
local build, neither on the CI)
https://github.com/llvm/llvm-project/pull/107408
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https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116636
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https://github.com/llvm/llvm-project/pull/118312
From e8c3d6da73e95fd03e5ccdf8e08bdc99ff52e6f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 2 Dec 2024 16:50:47 +0100
Subject: [PATCH 1/2] Revert "[SPIR-V] Fixup storage class for glo
@@ -3388,6 +3398,13 @@ bool SPIRVInstructionSelector::selectGlobalValue(
GVType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
}
+ const unsigned AddrSpace = GV->getAddressSpace();
+ SPIRV::StorageClass::StorageClass StorageClass =
+ addressSpaceToSto
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/116636
From 30bdda1649c1c9480968f830c326554f76eabdb6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Thu, 28 Nov 2024 15:00:56 +0100
Subject: [PATCH 1/2] [SPIR-V] Add hlsl_private address space for
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+@PrivInternal = internal addrspace(10) global i32 456
+; CHE
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116636
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@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
Oh didn't knew I could modify the target's AS maps without also modifying this.
I'll revert/re-land this PR (given the othe
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/118312
This reverts commit aa7fe1c10e5d6d0d3aacdb345fed995de413e142.
From e8c3d6da73e95fd03e5ccdf8e08bdc99ff52e6f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 2 Dec 2024 16:50:47 +0100
Su
@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
We hoped to split the PRs between back-end and FE, shall I land both at the
same time?
https://github.com/llvm/llvm-proje
https://github.com/Keenuts commented:
Thanks, answered the question for the intrinsic.
As Chris said, this would definitely needs to have some tests in the spir-v
backend.
Especially given that the structurizer assumes the selection control mask was
always `None`.
When splitting edges, or movin
@@ -2694,19 +2694,49 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
}
return MIB.constrainAllUses(TII, TRI, RBI);
}
- case Intrinsic::spv_loop_merge:
- case Intrinsic::spv_selection_merge: {
-const auto Opcode = IID == Intrinsic::spv_select
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116331
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https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/118651
Before this patch, there was a calling-convention mismatch between the
constructors and the actual call emitted for the entrypoint wrapper.
Such mismatch causes the InstCombine pass to replace this call with an
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm
-O3 -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -triple spirv-vulkan-compute -x hlsl -emit-llvm -O3 -o - %s
| FileCheck %s --check-prefixes=CHECK,CHECK
https://github.com/Keenuts approved this pull request.
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@@ -20440,6 +20442,26 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
}
}
+Value *CodeGenFunction::EmitSPIRVBuiltinExpr(unsigned BuiltinID,
+ const CallExpr *E) {
+ switch (BuiltinID) {
+ case SPIRV::BI__bui
@@ -0,0 +1,59 @@
+//===- SemaSPIRV.cpp - Semantic Analysis for SPIRV constructs
+//---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/Keenuts approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/121738
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https://github.com/Keenuts approved this pull request.
LGTM on the SPIR-V side. Just a superfluous loop thing.
For the structurizer, seems like this is OK, worst case we might end-up with a
new condition which has no Flatten/Dontflatten attachment but should be fine.
https://github.com/llvm/llv
@@ -2776,19 +2776,35 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
}
return MIB.constrainAllUses(TII, TRI, RBI);
}
- case Intrinsic::spv_loop_merge:
- case Intrinsic::spv_selection_merge: {
-const auto Opcode = IID == Intrinsic::spv_select
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116331
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@@ -1229,8 +1248,15 @@ FunctionPass *llvm::createSPIRVStructurizerPass() {
PreservedAnalyses SPIRVStructurizerWrapper::run(Function &F,
FunctionAnalysisManager &AF) {
- FunctionPass *StructurizerPass = createSPIRVStructurizerPas
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
https://github.com/Keenuts approved this pull request.
Maybe the renaming shall be done in another PR for both DXIL and SPV, but if
it's a small change, might want to do it now no?
https://github.com/llvm/llvm-project/pull/121963
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https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/121963
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@@ -118,6 +118,10 @@ let TargetPrefix = "spv" in {
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty, llvm_i8_ty],
[IntrInaccessibleMemOrArgMemOnly]>;
+ def int_spv_resource_getpointer
Keenuts wrote:
Shall it be `int_spv
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/122103
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https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/122103
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https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/122103
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https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/122103
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@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
That's correct, slightly reworded the description.
The thing is, only SPIR-V will be using this for now (same as the few ot
@@ -83,6 +84,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_private
---
@@ -83,6 +84,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_private
---
https://github.com/Keenuts approved this pull request.
SPIR-V failure is unrelated, known issue with ccache
https://github.com/llvm/llvm-project/pull/122105
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@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
This being a small stepping stone for the larger change bringing
hlsl_input/hlsl_output, I haven't wrote a specific HLSL s
@@ -83,6 +84,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_private
---
@@ -1468,9 +1468,14 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) {
// Set specific Vulkan version if applicable.
if (const Arg *A = Args.getLastArg(options::OPT_fspv_target_env_EQ)) {
- const llvm::StringSet<> ValidValues = {"vulkan1.2",
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/121961
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