================
@@ -204,7 +204,11 @@ addressSpaceToStorageClass(unsigned AddrSpace, const
SPIRVSubtarget &STI) {
? SPIRV::StorageClass::HostOnlyINTEL
: SPIRV::StorageClass::CrossWorkgroup;
case 7:
+ return SPIRV::StorageClass::Private;
+ case 8:
return SPIRV::StorageClass::Input;
----------------
Keenuts wrote:
No, that's something I need to clear with Intel regarding the LLVM SPIR-V
translator.
Right now, this is not used, so I don't know if that's something added but
never used, or if that's related to LLVM translator handling of those address
space.
(This can change, as we see in the Discourse threads about AS numbering change,
but if it's used in LLVM translator, I'd need to do it everywhere (in such case
I wouldn't change it, but keep the same number)
Anyway, the actual value is not important
https://github.com/llvm/llvm-project/pull/116393
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