lukel97 wrote:
Oh nice, I'm running into something similar in
https://github.com/llvm/llvm-project/pull/71657. Are all these dead ADDIs
instructions coming from the backwards local postpass?
https://github.com/llvm/llvm-project/pull/65934
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lukel97 wrote:
> > Oh nice, I'm running into something similar in #71657. Are all these dead
> > ADDIs coming from the backwards local postpass?
>
> Yes. I believe this PR can address the issue.
My suspicion is that these LIs only become dead because the backwards local
postpass deletes a vse
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/76942
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extens
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/76962
collectNonISAExtFeature was returning any negative extension features, e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative exte
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https://github.com/llvm/llvm-project/pull/76962
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>From dfaf782113b977c9960358adab88767e23ddbc56 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 20:48:09 +0700
Subject: [PATCH] [RISCV] Fix collectNonISAExtFeature returning negative
extension featu
lukel97 wrote:
Note that this doesn't fix the issue described in
https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559.
One approach that would build upon this would be to use the entire list of
target features including negative extensions when a full arch string is
sp
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76962
>From dfaf782113b977c9960358adab88767e23ddbc56 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 20:48:09 +0700
Subject: [PATCH 1/2] [RISCV] Fix collectNonISAExtFeature returning negative
extension f
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/2] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/3] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/4] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/5] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
@@ -42,9 +42,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ const auto ISAInfoFeatures = (
@@ -466,35 +466,35 @@ bool RISCVISAInfo::compareExtension(const std::string
&LHS,
return LHS < RHS;
}
-void RISCVISAInfo::toFeatures(
-std::vector &Features,
-llvm::function_ref StrAlloc,
-bool AddAllExtensions) const {
- for (auto const &Ext : Exts) {
-Str
Author: Luke Lau
Date: 2024-01-08T16:04:33+07:00
New Revision: 2c213c45046b78eac48809b013e7a80099607ebb
URL:
https://github.com/llvm/llvm-project/commit/2c213c45046b78eac48809b013e7a80099607ebb
DIFF:
https://github.com/llvm/llvm-project/commit/2c213c45046b78eac48809b013e7a80099607ebb.diff
LOG:
https://github.com/lukel97 closed
https://github.com/llvm/llvm-project/pull/76962
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https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77327
In #77277, we would like to be able to reuse the logic for calculating the
vscale_range in Flang. This is currently in clang::TargetInfo which is quite C
specific, and given that only two targets implement getVSca
https://github.com/lukel97 edited
https://github.com/llvm/llvm-project/pull/77327
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https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/6] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From e0b653a5f81d18155583f6dfd669003b6664a517 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/6] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
https://github.com/lukel97 closed
https://github.com/llvm/llvm-project/pull/76942
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https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77426
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch str
lukel97 wrote:
> I'm wondering if you considered moving the helper function into RISCVISAInfo?
Initially yes, but I ended up backing out of it since it would have been the
only bit of "codegen" logic in RISCVISAInfo, and it seemed a shame to pollute
it.
I also have a feeling that we will need
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/4] [RISCV] Add support for new unprivileged extensions
defined in pro
lukel97 wrote:
@asb I got a response from https://github.com/riscv/riscv-profiles/issues/139,
looks like Ziccrse, Ziccamoa, Za64rs, and Za128rs don't imply A.
https://github.com/llvm/llvm-project/pull/77458
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https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/5] [RISCV] Add support for new unprivileged extensions
defined in pro
lukel97 wrote:
> These names will be used in profiles only, but I don't know if we should add
> them to RISCVUsage.rst.
Good point, I added them in anyway so we're consistent at least. I couldn't
find any other "featureless" extensions that we currently support.
https://github.com/llvm/llvm-p
@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS
Support
TargetParser
FrontendOpenMP
+ FrontendDriver
lukel97 wrote:
I agree. I think I'm coming around to the opinion that this is a bit overkill
just to avoid duplicating 16 lines of code.
I'm also thinking th
@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS
Support
TargetParser
FrontendOpenMP
+ FrontendDriver
lukel97 wrote:
I think the issue with llvmFrontendDriver specifically is that this code
wouldn't be called from any of the drivers, it would be called from cl
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77588
This patch adds support for the -mrvv-vector-bits flag in the Flang driver, and
translates them to -mvscale-min/-mvscale-max.
The code was copied from the Clang toolchain (similarly to what was done for
AArch64's
https://github.com/lukel97 edited
https://github.com/llvm/llvm-project/pull/77458
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https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/6] [RISCV] Add support for new unprivileged extensions
defined in pro
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77588
>From 66f47b300afa5f68934c93fed0b16d7a389cf49d Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Wed, 10 Jan 2024 18:22:03 +0700
Subject: [PATCH 1/2] [Flang] Support -mrvv-vector-bits flag
This patch adds support fo
https://github.com/lukel97 closed
https://github.com/llvm/llvm-project/pull/77588
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https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77645
We have two structs for representing the version of an extension in
RISCVISAInfo, with the exact same fields. This patch deduplicates them.
> [!NOTE]
> When renaming the struct, I also dropped the struct's name f
https://github.com/lukel97 edited
https://github.com/llvm/llvm-project/pull/77645
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https://github.com/llvm/llvm-project/pull/77645
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https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77645
>From 916d4f271982501b7236d60b90c9fa822f7aa2a6 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 11 Jan 2024 00:44:19 +0700
Subject: [PATCH 1/2] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC
We have t
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77645
>From 916d4f271982501b7236d60b90c9fa822f7aa2a6 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 11 Jan 2024 00:44:19 +0700
Subject: [PATCH 1/3] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC
We have t
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in pro
https://github.com/lukel97 closed
https://github.com/llvm/llvm-project/pull/77645
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https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 8de2b22ba2723fccf16ca4d2a863f84fd1b66493 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in pro
lukel97 wrote:
Rebased on top of 79889fedc57707e99740abc1f48e6c5601d5a3f3
https://github.com/llvm/llvm-project/pull/77458
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https://github.com/lukel97 closed
https://github.com/llvm/llvm-project/pull/77327
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lukel97 wrote:
Closing for now as deduplication the clang/flang frontend logic most likely
requires more thought and discussion
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@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
lukel97 wrote:
Can this land until #85790 lands?
https://github.com/llvm/llvm-project/pull/85786
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@@ -326,6 +326,48 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp) &&
+ LT.second.getVectorElementType() != MVT::i1) {
+unsigned TpReg
@@ -326,6 +326,48 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp) &&
+ LT.second.getVectorElementType() != MVT::i1) {
+unsigned TpReg
@@ -764,6 +771,58 @@ def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
"'Smepmp' (Enhanced Physical Memory Protection)", []>;
+def FeatureStdExtSsccptr
+: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
+
@@ -91,9 +91,24 @@ on support follow.
``E``Supported (`See note <#riscv-rve-note>`__)
``H``Assembly Support
``M``Supported
+ ``Shcounterenw`` Assembly Support
+ ``Shgatpa`` Assembly Support
+ ``Shtvala`` A
@@ -91,9 +91,24 @@ on support follow.
``E``Supported (`See note <#riscv-rve-note>`__)
``H``Assembly Support
``M``Supported
+ ``Shcounterenw`` Assembly Support
+ ``Shgatpa`` Assembly Support
+ ``Shtvala`` A
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/2] [RISCV] Overwrite cpu target features for full arch
string in targ
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/3] [RISCV] Overwrite cpu target features for full arch
string in targ
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension tar
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/4] [RISCV] Overwrite cpu target features for full arch
string in targ
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From fb8eebe1c7f5b4dec812c64d9a2572a98d59bdb8 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in pro
Author: Luke Lau
Date: 2024-01-18T21:47:06+07:00
New Revision: 9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64
URL:
https://github.com/llvm/llvm-project/commit/9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64
DIFF:
https://github.com/llvm/llvm-project/commit/9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64.diff
LOG:
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From d22817bcd7ea7ab5763cb4da58552ce6930d4b73 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in pro
lukel97 wrote:
Rebased on top of 9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64 which should fix the
pre-merge check test failure
https://github.com/llvm/llvm-project/pull/77458
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lukel97 wrote:
Hi, I'm no longer able to compile SPEC CPU 2017 after this due to an error in
510.parest_r:
```
/cpu2017/benchspec/CPU/510.parest_r/src/source/fe/fe_tools.cc:2020:15: error:
partial ordering for explicit instantiation of 'back_interpolate' is ambiguous
2020 | void FETools::back
lukel97 wrote:
@mizvekov
I'm not sure if it's possible to share SPEC sources due to the license, but
creduce was able to get it down to this which passed with -fsyntax-only before
aa7497a.
```c++
template class a;
template class b;
class c {
template
void h(const a &, const e &, const
lukel97 wrote:
Here's the version without the rename pass
```c++
template class DoFHandler;
template class FiniteElement;
class FETools {
template
void back_interpolate(const DoFHandler &, const InVector &,
const FiniteElement &, OutVector &);
template class DH,
lukel97 wrote:
I just checked and gcc-13 is able to build that SPEC benchmark fine, so I think
you're right there's probably some macro somewhere. I'll go digging for around
for it.
https://github.com/llvm/llvm-project/pull/100692
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lukel97 wrote:
I did a bit of grepping but I couldn't find any obvious macro. But I realised
that gcc actually does accept the reproducer, when compiled with
`-std=gnu++98`: https://compiler-explorer.com/z/zsGY6xbh5
This flag is set when compiling SPEC, and seems to be where clang differs.
h
lukel97 wrote:
I tried out #94981 and -fno-relaxed-template-template-args and can confirm both
fix it. I'm now running into a separate LoopVectorizer crash, but I made it out
of the frontend :)
Using -fno-relaxed-template-template-args should be fine, in llvm-test-suite we
already do somethin
lukel97 wrote:
I'm also seeing a error when building the 510.parest_r benchmark from SPEC CPU
2017
https://github.com/llvm/llvm-project/pull/98547
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lukel97 wrote:
Hi, this seems to uncover an unfortunate error in xalan-c
https://github.com/apache/xalan-c/blob/c326619da4813acfc845c2830d904a4860f9afe1/src/xalanc/XMLSupport/XalanOtherEncodingWriter.hpp#L323
which is present in one of the SPEC CPU 2017 benchmarks (and prevents SPEC CPU
2017 f
https://github.com/lukel97 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/92167
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lukel97 wrote:
> > I tried out #94981 and -fno-relaxed-template-template-args and can confirm
> > both fix it. I'm now running into a separate LoopVectorizer crash, but I
> > made it out of the frontend :)
> > Using -fno-relaxed-template-template-args should be fine, in
> > llvm-test-suite we
@@ -205,14 +288,60 @@ uses the function `buffer-file-name'."
(delete-file temp-file)
(when (buffer-name temp-buffer) (kill-buffer temp-buffer)
+;;;###autoload
+(defun clang-format-git-diffs (&optional style assume-file-name)
lukel97 wrote:
I t
@@ -146,18 +146,104 @@ is a zero-based file offset, assuming ‘utf-8-unix’
coding."
(lambda (byte &optional _quality _coding-system)
(byte-to-position (1+ byte)
-;;;###autoload
-(defun clang-format-region (start end &optional style assume-file-name)
- "Use clang
@@ -26,5 +26,5 @@ entry:
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
declare @llvm.masked.gather.nxv4i32.nxv4p0(, i32 immarg, , ) #1
-attributes #0 = {
"target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve
@@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
lukel97 wrote:
Just a heads up I've been using this locally for a bit now and it's been great,
thanks for working on this. Haven't run into any issues so far.
https://github.com/llvm/llvm-project/pull/112792
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https://github.com/lukel97 approved this pull request.
Apologies for the delay on this again. However I tried it out locally and it
now seems to work on macOS, thanks for fixing that!
I really can't speak much for the elisp, but we don't have many reviewers for
the emacs stuff and this featur
@@ -194,7 +194,7 @@ void for_test_scalable(int *List, int Length) {
}
}
-// Verify for loop is performing scalable vectorization
+// Verify for loop is NOT performing vectorization because the width is 1
lukel97 wrote:
> If taking the intent of the original
https://github.com/lukel97 approved this pull request.
Thanks, LGTM. Though this is a part of the code that I'm not familiar with so
probably best to wait for another LGTM
https://github.com/llvm/llvm-project/pull/135163
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