https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76962
>From dfaf782113b977c9960358adab88767e23ddbc56 Mon Sep 17 00:00:00 2001
From: Luke Lau <l...@igalia.com>
Date: Thu, 4 Jan 2024 20:48:09 +0700
Subject: [PATCH] [RISCV] Fix collectNonISAExtFeature returning negative
extension features
collectNonISAExtFeature was returning any negative extension features, e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative extensions aren't emitted when calling toFeatureVector(), and
so were considered missing. Hence why we still see "-zfa" and "-zfb" in the
tests for the full arch string attributes, even though with a full arch string
we should be overriding the extensions.
This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead to
check if a feature is an ISA extension.
---
clang/lib/Basic/Targets/RISCV.cpp | 19 ++++++-------------
.../CodeGen/RISCV/riscv-func-attr-target.c | 8 ++++----
2 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..b98cd093bc9b0e 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -237,22 +237,15 @@ ArrayRef<Builtin::Info>
RISCVTargetInfo::getTargetBuiltins() const {
static std::vector<std::string>
collectNonISAExtFeature(ArrayRef<std::string> FeaturesNeedOverride, int XLen) {
- auto ParseResult =
- llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride);
-
- if (!ParseResult) {
- consumeError(ParseResult.takeError());
- return std::vector<std::string>();
- }
-
- std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatureVector();
-
std::vector<std::string> NonISAExtFeatureVec;
+ auto IsNonISAExtFeature = [](const std::string &Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ std::string Ext = Feature.substr(1); // drop the +/-
+ return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+ };
llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
- [&](const std::string &Feat) {
- return !llvm::is_contained(ImpliedFeatures, Feat);
- });
+ IsNonISAExtFeature);
return NonISAExtFeatureVec;
}
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 506acaba687417..759c33a2250600 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -40,8 +40,8 @@ __attribute__((target("cpu=sifive-u54"))) void
testAttrCpuOnly() {}
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa"
}
// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
-// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax,-zfa"
}
-// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
+// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax"
}
+// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax" }
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax,-zbb,-zfa"
}
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax"
}
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