[PATCH] D49674: [AArch64] Add Tiny Code Model for AArch64

dmgreen added a comment. Thanks https://reviews.llvm.org/D49674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49674: [AArch64] Add Tiny Code Model for AArch64

This revision was automatically updated to reflect the committed changes. Closed by commit rC340398: [AArch64] Add Tiny Code Model for AArch64 (authored by dmgreen, committed by ). Repository: rC Clang https://reviews.llvm.org/D49674 Files: include/clang/Driver/CC1Options.td lib/CodeGen/B

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen created this revision. dmgreen added reviewers: SjoerdMeijer, hfinkel, tyler.nowicki, anemet, alexfh. Herald added a subscriber: zzheng. This adds support for the unroll_and_jam pragma, to go with https://reviews.llvm.org/D41953. The name of the pragma is copied from the Intel compiler, a

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen added a comment. > In my experience, they are used. Good to know, cheers. > Could we maybe disable the #pragma clang loop unroll_and_jam spelling ftm to > avoid compatibility issues? Sure, I'm not against. It sounds like you have opinions on how this should work. That's good. If there

[PATCH] D47320: [UnrollAndJam] Add pragma clang loop unroll_and_jam handling.

dmgreen created this revision. Herald added a subscriber: zzheng. Split out from https://reviews.llvm.org/D47267 when we need it. https://reviews.llvm.org/D47320 Files: include/clang/Basic/DiagnosticParseKinds.td lib/Parse/ParsePragma.cpp lib/Sema/SemaStmtAttr.cpp test/CodeGenCXX/pragma

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen updated this revision to Diff 148393. dmgreen added a comment. This splits out the pragma clang loop unroll_and_jam handling into https://reviews.llvm.org/D47320, for if/when we need it. Which I believe is what you wanted, correct me if I'm wrong. https://reviews.llvm.org/D47267 Files

[PATCH] D51416: [RTTI] Align rtti type string to prevent over-alignment

dmgreen created this revision. dmgreen added reviewers: efriedma, echristo, hfinkel, davide. Previously the alignment on the newly created rtti string was not set, meaning that DataLayout::getPreferredAlignment was free to overalign it to 16 bytes. This causes unnecessary code bloat. https://rev

[PATCH] D51416: [RTTI] Align rtti types to prevent over-alignment

dmgreen updated this revision to Diff 163727. dmgreen retitled this revision from "[RTTI] Align rtti type string to prevent over-alignment" to "[RTTI] Align rtti types to prevent over-alignment". dmgreen edited the summary of this revision. dmgreen added a comment. I've become less sure about wha

[PATCH] D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89

dmgreen added a comment. These new changes look good to me. If you are updating things like this, it's often better to create a new Phab review so it's easier to see it's a new thing (or, in cases like this where the changes are simple and just test updates, they often don't need review). Eithe

[PATCH] D51416: [RTTI] Align rtti types to prevent over-alignment

dmgreen updated this revision to Diff 164693. dmgreen added a comment. Now using getABITypeAlignment, plus added a simple test https://reviews.llvm.org/D51416 Files: lib/CodeGen/CGVTT.cpp lib/CodeGen/CGVTables.cpp lib/CodeGen/CodeGenModule.cpp lib/CodeGen/CodeGenModule.h lib/CodeGen/I

[PATCH] D51416: [RTTI] Align rtti types to prevent over-alignment

dmgreen added a comment. That sounds like a good idea. Thanks for the help on this one. https://reviews.llvm.org/D51416 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51416: [RTTI] Align rtti types to prevent over-alignment

This revision was automatically updated to reflect the committed changes. Closed by commit rL342053: [CodeGen] Align rtti and vtable data (authored by dmgreen, committed by ). Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D51416?vs=164693&id=165077#t

[PATCH] D49674: [AArch64] Add Tiny Code Model for AArch64

dmgreen created this revision. dmgreen added reviewers: t.p.northover, olista01, john.brawn. Herald added a reviewer: javed.absar. Herald added a subscriber: kristof.beyls. Adds a tiny code model as a Clang side of https://reviews.llvm.org/D49673. https://reviews.llvm.org/D49674 Files: includ

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen updated this revision to Diff 158219. dmgreen added a comment. Rebase. Michael, you happy with this part? The pragma clang loop part is off in https://reviews.llvm.org/D47320. Let me know if/when I should do something with that. https://reviews.llvm.org/D47267 Files: include/clang/

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

This revision was automatically updated to reflect the committed changes. Closed by commit rC338566: [UnrollAndJam] Add unroll_and_jam pragma handling (authored by dmgreen, committed by ). Changed prior to commit: https://reviews.llvm.org/D47267?vs=158219&id=158537#toc Repository: rC Clang

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen added a comment. Thanks. Repository: rC Clang https://reviews.llvm.org/D47267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen added a comment. Thanks. I noticed in the paper that you used the name "unrollandjam", minus underscores. Should I change this use that spelling here? I have no strong opinion of one over the other (was just using what I had found from the Intel docs). https://reviews.llvm.org/D47267

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen added a comment. I quite like the UnrollAndFuse naming. I'd not heard that the xlc compiler called it that. The UnrollAndJam pass was origin named that before I renamed for similar reasons (UnrollAndJam being more well known). I see your point about the mix of underscores. "nounroll_and

[PATCH] D47267: [UnrollAndJam] Add unroll_and_jam pragma handling

dmgreen added a comment. In https://reviews.llvm.org/D47267#1123318, @hfinkel wrote: > I have a preference for using the underscores as our primary spelling. I > think that it's easier to read. I agree with it being easier to read. > I prefer we have a different syntax that we can use consist

[PATCH] D57978: [CodeGen] Generate follow-up metadata for loops with more than one transformation.

dmgreen added a comment. Hello. I also don't feel very familiar with clang, but had a poke around and I think it looks pretty good. I see unroll and jam is being awkward again. This could maybe do with a few extra tests. Am I correct in saying something like this: #pragma unroll_and_jam(4)

[PATCH] D57978: [CodeGen] Generate follow-up metadata for loops with more than one transformation.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Yeah, OK. This looks like a good patch to me. As I said, I'm not a clang expert, but the code looks sensible enough. (Perhaps wait a couple of days in case others have objections.) Reposit

[PATCH] D59879: [ARM][CMSE] Add commandline option and feature macro

dmgreen added reviewers: olista01, christof. dmgreen added inline comments. Comment at: include/clang/Driver/Options.td:2145 + Flags<[DriverOption,CC1Option]>, + HelpText<"Allow use of CMSE instructions (ARM only)">; Should this say something about compiling

[PATCH] D60691: [ARM] Replace fp-only-sp and d16 with fp64 and d32.

dmgreen added a comment. I don't think we here care about auto-updating, not supporting bitcode/lto libraries. Comment at: llvm/lib/Target/ARM/ARMFastISel.cpp:1362 + if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64())) + return false; --

[PATCH] D62729: [ARM] Fix recent breakage of -mfpu=none.

dmgreen added inline comments. Comment at: clang/test/CodeGen/arm-mfpu-none.c:2 +// REQUIRES: arm-registered-target +// RUN: %clang -target arm-none-eabi -mcpu=cortex-m4 -mfpu=none -S -o - %s | FileCheck %s + lebedev.ri wrote: > Generally clang codegen tests sho

[PATCH] D62729: [ARM] Fix recent breakage of -mfpu=none.

dmgreen added inline comments. Comment at: clang/test/CodeGen/arm-mfpu-none.c:2 +// REQUIRES: arm-registered-target +// RUN: %clang -target arm-none-eabi -mcpu=cortex-m4 -mfpu=none -S -o - %s | FileCheck %s + simon_tatham wrote: > dmgreen wrote: > > lebedev.ri w

[PATCH] D62729: [ARM] Fix recent breakage of -mfpu=none.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. LGTM. Thanks for adding the new test. I agree with keeping both tests ( I wasn't very clear). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62

[PATCH] D60710: [ARM] Add ACLE feature macros for MVE.

dmgreen added a comment. Hello. Hopefully fixed in rC362814 ! Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60710/new/ https://reviews.llvm.org/D60710 ___ cfe-commits mailing list cf

[PATCH] D59879: [ARM][CMSE] Add commandline option and feature macro

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. LGTM. With one comment that I will leave to you for what you think is best. Comment at: include/clang/Driver/Options.td:2145 + Flags<[DriverOption,CC1Option]>, + HelpText

[PATCH] D67160: [clang, ARM] Default to -fno-lax-vector-conversions in ARM v8.1-M.

dmgreen added a comment. FYI: rL371817 , in case it changes what is done here. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67160/new/ https://reviews.llvm.org/D67160 _

[PATCH] D62394: [ARM][CMSE] Add CMSE header & builtins

dmgreen added a subscriber: chill. dmgreen added a comment. I'm afraid the upstreaming of CMSE has stalled, and this is not all that would be needed to get it working. This adds some header files and clang builtins, the selection of them in the backend isn't yet present, hence the error you are

[PATCH] D67161: [clang,ARM] Initial ACLE intrinsics for MVE.

dmgreen added a comment. Sorry. I wasn't ignoring this (sort-of), I just knew that you were on holiday and this is a bit of a big one. But I like this. I still have to take a deeper look into the main tablegen parts, but it looks very powerful. I presume from here adding new intrinsics is most

[PATCH] D67161: [clang,ARM] Initial ACLE intrinsics for MVE.

dmgreen added inline comments. Comment at: clang/include/clang/Basic/arm_mve_defs.td:119 +// The type Void can be used for the return type of an intrinsic, and as the +// parameter type for intrinsics that aren't actually parametrised by any kind +// of _s32 / _f16 / _u8 suffix.

[PATCH] D67161: [clang,ARM] Initial ACLE intrinsics for MVE.

dmgreen added subscribers: samparker, SjoerdMeijer. dmgreen added a comment. This is looking good to me. My understanding is that is has some dependencies? The llvm side will likely needed to go in first, plus a couple of clang patches? Comment at: clang/include/clang/Basic/Di

[PATCH] D67160: [clang, ARM] Default to -fno-lax-vector-conversions in ARM v8.1-M.

dmgreen added a comment. Yes.. My understanding is that the default is still -flax-vector-convertions=all (the old clang behaviour), but the plan is to change it (for all architectures) to none. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67160/

[PATCH] D67160: [clang, ARM] Default to -fno-lax-vector-conversions in ARM v8.1-M.

dmgreen added a subscriber: rsmith. dmgreen accepted this revision. dmgreen added a comment. Yeah, OK. D67678 is the patch that will change the default, but only to "int", not to "none" for the moment. An earlier version of that patch had a different way of sett

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

dmgreen added subscribers: samparker, dmgreen. dmgreen added a comment. Sam has been looking at extending masked loads and stores in D68337 and related patches. There looks like there would be some overlap with this, especially in the target independent parts.

[PATCH] D69025: [Driver,ARM] Make -mfloat-abi=soft turn off MVE.

dmgreen added a comment. I do not know this code super well. What happens to the preprocessor in such cases? Does it disable the relevant macros automatically because we've turned off the mve and mve.fp features? Could you add a test? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D69025: [Driver,ARM] Make -mfloat-abi=soft turn off MVE.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Yeah, OK. That makes sense. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69025/new/ https://reviews.llvm.org/D69025 ___

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

dmgreen added a comment. Thanks! It looks like the only supported parameter of the PassThru here is a splat of 0 or undef. This might get in the way of IR level optimisation that could try to producing a masked load with different passthru, which would then fail to select. The ARM backed added

[PATCH] D67161: [clang,ARM] Initial ACLE intrinsics for MVE.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. I've read this through again and it looks good. If no one else has any issues, then LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67161/

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. In D68877#1718729 , @kmclaughlin wrote: > There is not yet support for vector selects, so for this patch the intention > was that any passthru which

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Looks good to me. (Stores are easier than loads) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69378/new/ https://reviews.llvm.org/D69378 _

[PATCH] D67161: [clang,ARM] Initial ACLE intrinsics for MVE.

dmgreen added a comment. Hmm.. Let me take a look. There's a different error on the same build now, but I think it's just hiding this one. I'll also try and fix the tests that are failing in places too, if I can. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D67161: [clang,ARM] Initial ACLE intrinsics for MVE.

dmgreen added a comment. I've hopefully fixed the build in rG7b3de1e81197 , but it's hard to tell for sure with the other error. I also fixed the tests in rG78700ef8866d

[PATCH] D69426: [clang] Switch arm-mve-intrinsics tests to use %clang_cc1.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Sounds good. But make sure that -fno-discard-value-names is still included. Otherwise the names like "entry" will not be output, so the tests fail in "non-assert" builds. Repository: rG

[PATCH] D69426: [clang] Switch arm-mve-intrinsics tests to use %clang_cc1.

dmgreen added a comment. Ah, I see, that's why it was needed. That makes sense. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69426/new/ https://reviews.llvm.org/D69426 ___ cfe-commits mailing list cfe

[PATCH] D79710: [clang][BFloat] add create/set/get/dup intrinsics

dmgreen added inline comments. Comment at: clang/include/clang/Basic/arm_neon.td:1860 + + def VGET_HIGH_BF : NoTestOpInst<"vget_high", ".Q", "b", OP_HI>; + def VGET_LOW_BF : NoTestOpInst<"vget_low", ".Q", "b", OP_LO>; Do you know what InstName = "vmov" does, a

[PATCH] D81728: [InstCombine] Add target-specific inst combining

dmgreen added inline comments. Comment at: llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: opt -instcombine %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o -

[PATCH] D81728: [InstCombine] Add target-specific inst combining

dmgreen added a comment. Thanks Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81728/new/ https://reviews.llvm.org/D81728 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[PATCH] D78252: [AArch64] FMLA/FMLS patterns improvement.

dmgreen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8055 multiclass SIMDFPIndexedTiedPatterns { + let Predicates = [HasNEON, HasFullFP16] in { + // 1 variant for the .8h version: DUPLANE from 128-bit Should we have equal p

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

dmgreen added reviewers: efriedma, ostannard, SjoerdMeijer. dmgreen added a comment. Love it. This will help optimise these more too. We can currently get into places where we can't prove only the bottom bits of a returned value are demanded so can't remove unnecessary vmovs. Test look good too

[PATCH] D82887: [ARM] Add Cortex-A77 Support for Clang and LLVM

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82887/new/ https://reviews.llvm.org/D82887 ___ cfe-commits mailing list cf

[PATCH] D83206: [PATCH] [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM

dmgreen added a comment. I would expect this to be very similar to https://reviews.llvm.org/rG8bf99f1e6f0f9b426d6060361ea6d9d47c1868d1, but some parts seems to be missing. Can you make sure that everything is included and in a sensible order. Comment at: llvm/include/llvm/Su

[PATCH] D82574: Merge TableGen files used for clang options

dmgreen added a comment. Hello Did you mean to remove CC1Options.td too? Otherwise it does not appear to be used any more or this has duplicated the contents. Also can you make sure the new content of Options.td reflects the latest version of CC1Options.td, and that no extra changes have been

[PATCH] D83206: [PATCH] [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM

dmgreen added inline comments. Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:135 + (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | + AArch64::AEK_SSBS | AArch64::AEK_RAS)) AARCH64_CPU_NAME("neoverse-e1", ARMV8_2A,

[PATCH] D83206: [PATCH] [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83206/new/ https://reviews.llvm.org/D83206 ___ cfe-commits mailing list cfe

[PATCH] D82887: [ARM] Add Cortex-A77 Support for Clang and LLVM

dmgreen added reviewers: dmgreen, ostannard, SjoerdMeijer. dmgreen added a comment. Please make sure the switch in AArch64Subtarget::initializeProperties has an entry too. Do you happen to know the cpu id for host.cpp? Comment at: clang/test/Driver/aarch64-cpus.c:729 +// RU

[PATCH] D78252: [AArch64] FMLA/FMLS patterns improvement.

dmgreen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8055 multiclass SIMDFPIndexedTiedPatterns { + let Predicates = [HasNEON, HasFullFP16] in { + // 1 variant for the .8h version: DUPLANE from 128-bit ilinpv wrote: > dmgree

[PATCH] D78252: [AArch64] FMLA/FMLS patterns improvement.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. LGTM. Thanks Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8094 V128:$Rm, VectorIndexS:$idx)>; - def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32

[PATCH] D77872: [AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics

dmgreen added inline comments. Comment at: llvm/lib/Target/ARM/ARMInstrNEON.td:4846 + VDOT { + let hasNoSchedulingInfo = 1; + I don't think that hasNoSchedulingInfo is necessarily the best way to handle this. That flag is intended for instructions that wil

[PATCH] D77872: [AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics

dmgreen added inline comments. Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Comment at: llvm/lib/Target/ARM/ARMInstrNEON.td:4846 + VDOT { + let hasNoSchedulingInfo = 1; + LukeGeeson wrote: > dmgreen wrote: > > I don't think that ha

[PATCH] D85575: [ARM] Speed up arm-cortex-cpus.c test

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Yeah, nice. Sounds good to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D85575/new/ https://reviews.llvm.org/D85575 _

[PATCH] D155688: [PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP

dmgreen added a comment. I hadn't realized this came from someone at Arm. The performance results I had were overall roughly flat, with some improvements and regressions. I think there were still some people working through some fixes for some of the knock-on effects but with those nothing larg

[PATCH] D128415: [ARM] Add Support for Cortex-M85

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Other than the release note change it might be worth adding some tests for -mcpu=cortex-m85+nopacbti and related configurations. Otherwise LGTM Comment at: clang/docs/Rel

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

dmgreen added inline comments. Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:145 + case ARM::VMVNq: +return CondCodeIsAL(3); + // VMOV of 64-bit value between D registers (when condition = al) Can/should all these use findFirstPredOperan

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

dmgreen added inline comments. Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:200-207 + case ARM::VMOVv2f32: + case ARM::VMOVv4f32: + case ARM::VMOVv2i32: + case ARM::VMOVv4i32: + case ARM::VMOVv4i16: + case ARM::VMOVv8i16: + case ARM::VMOVv8i8:

[PATCH] D130973: [AArch64] Always allow the __bf16 type

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8c30f4a5ab3e: [AArch64] Always allow the __bf16 type (authored by dmgreen). Herald added a project: clang. Herald added a subscriber: cfe-commits. R

[PATCH] D127812: [AArch64] Function multiversioning support added.

dmgreen added inline comments. Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:188 +AARCH64_CPU_FEATURE("sve_aes",SVE_AES, "+sve2-aes", 330) +AARCH64_CPU_FEATURE("sve_pmull128", SVE_PMULL128, "", 340) +AARCH64_CPU_FEATURE("sve_bitperm",

[PATCH] D120527: [OpaquePtr][AArch64] Use elementtype on ldxr/stxr

dmgreen added a comment. Seems OK. Thanks for the patch. Do opaque pointer variants (like `i32 @llvm.aarch64.stxr.p0(i64 1, ptr elementtype(i64) %ptr.0)`) get tested automatically from the existing tests once -opaque-pointers is the default? Repository: rG LLVM Github Monorepo CHANGES SINC

[PATCH] D121792: [AArch64][SVE] InstCombine llvm.aarch64.sve.sel to select

dmgreen added a comment. Why do we have llvm.aarch64.sve.sel if we are always going to replace it with a select? Why not remove llvm.aarch64.sve.sel entirely? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121792/new/ https://reviews.llvm.org/D1217

[PATCH] D122046: [clang] Remove Address::deprecated from MveEmitter

dmgreen added a reviewer: simon_tatham. dmgreen added a comment. > I'm very out of my depth with tablegen, let me know if there's a more elegant > way of doing this I think this sounds OK. Providing all the tests pass it looks OK (but I'm not a big expert myself) Repository: rG LLVM Github

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

dmgreen added a comment. Looks OK to me, as far as I can see. If it worth adding a few extra instructions that may come up? Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:146 + case ARM::VMVNd: + case ARM::VMVNq: + // VMOV of 64-bit value between D regist

[PATCH] D115620: [AArch64] Lowering and legalization of strict FP16

dmgreen added a comment. I might have misunderstood which this patch was. Can you move the clang test into D118259 with the other? It seems like the same problem, and it looks like there should be enough llc tests to cover all the cases. Co

[PATCH] D115620: [AArch64] Lowering and legalization of strict FP16

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. OK Thanks. This LGTM then. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115620/new/ https://reviews.llvm.org/D115620 ___ cfe-commits ma

[PATCH] D118257: [AArch64] Generate fcmps when appropriate for neon intrinsics

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. This seems OK. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118257/new/ https://reviews.llvm.org/D118257 __

[PATCH] D118044: [ARM] Undeprecate complex IT blocks

dmgreen added a comment. The actual code change looks fine to me, providing we can clean up these test changes a bit and no-one else has any other comments. Comment at: llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll:196 ; Hard-coded registers comes from the ABI. ; CHECK-LA

[PATCH] D118044: [ARM] Undeprecate complex IT blocks

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks for the updates. LGTM. Comment at: llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll:21 -; CHECK: bb.2.bb2: +; CHECK: bb.1.bb: ; CHECK: successors: %bb.4(0x4000),

[PATCH] D117795: [AArch64] Add some missing strict FP vector lowering

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks for the changes. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117795/new/ https://reviews.llvm.org/D117795 ___ cfe-commits

[PATCH] D117112: [AArch64] Support for Ampere1 core

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. I don't know the details of the scheduling latencies for the core, but this looks perfectly sensible. There are a few comments inline, but other than those this patch LGTM. ==

[PATCH] D117112: [AArch64] Support for Ampere1 core

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG64816e68f441: [AArch64] Support for Ampere1 core (authored by philipp.tomsich, committed by dmgreen). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

dmgreen added inline comments. Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:146 + case ARM::VMVNd: + case ARM::VMVNq: + // VMOV of 64-bit value between D registers (when condition = al) lenary wrote: > dmgreen wrote: > > Perhaps add these,

[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119720/new/ https://reviews.llvm.org/D119720 _

[PATCH] D125604: [FileCheck] Catch missspelled directives.

dmgreen added inline comments. Comment at: llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll:682-688 +; TODO-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h +; TODO-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h +; TODO-CVT-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] +; TODO-CVT-DAG:

[PATCH] D72270: [ARM,MVE] Fix many signedness errors in MVE intrinsics.

dmgreen added inline comments. Comment at: clang/include/clang/Basic/arm_mve.td:204 let params = T.Float in { - defm vminnmq : VectorVectorArithmetic<"min_predicated">; - defm vmaxnmq : VectorVectorArithmetic<"max_predicated">; + defm vminnmq : VectorVectorArithmetic<"min_pre

[PATCH] D72270: [ARM,MVE] Fix many signedness errors in MVE intrinsics.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. OK. LGTM then. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72270/new/ https://reviews.llvm.org/D72270 ___

[PATCH] D72268: [ARM,MVE] Support -ve offsets in gather-load intrinsics.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72268/new/ https://reviews.llvm.org/D72268

[PATCH] D72329: [ARM, MVE] Intrinsics for variable shift instructions.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. I imagine trying to read what a llvm.arm.mve.vshl means in IR would be quite difficult, but it does make lowering them simpler. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAS

[PATCH] D72328: [ARM,MVE] Intrinsics for partial-overwrite imm shifts.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. LGTM I think Comment at: clang/utils/TableGen/MveEmitter.cpp:1105 +int Num = Op->getValueAsInt("num"), Denom = Op->getValueAsInt("denom"); +unsigned desiredSize = S

[PATCH] D72444: [ARM,MVE] Fix valid immediate range for vsliq_n.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Nice test. LGTM Comment at: clang/test/Sema/arm-mve-immediates.c:182 + + vshrq(vb, 0); // expected-error {{argument value 0 is outside the valid range [1, 8]}} + vshrq(v

[PATCH] D72496: [ARM,MVE] Make `vqrshrun` generate the right instruction.

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Yeah, I said these would be tough to read! LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72496/new/ https://reviews.llvm.org/D72496 __

[PATCH] D72761: [ARM][MVE][Intrinsics] Add VMINAQ, VMINNMAQ, VMAXAQ, VMAXNMAQ intrinsics.

dmgreen added a comment. Nice one. Good to see codegen changes coming out of these intrinsics. It took a while for me to figure out what the integer instruction was doing. That's a strange one. The fp case I have a question about below. Comment at: llvm/lib/Target/ARM/ARMIns

[PATCH] D87972: [OldPM] Pass manager: run SROA after (simple) loop unrolling

dmgreen added a comment. > @dmgreen for arm?:) This would seem more like a good general codegen cleanup than something that would be target dependent. It would probably be more dependent on the code that is being run, than the exact target. But yeah, I ran some baremetal tests. Only one change

[PATCH] D86146: [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics

dmgreen added a comment. Do we need to upgrade the old bfmmla to the new signatures? Comment at: llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll:176 - -define <4 x float> @test_vbfmlaltq_laneq_f32_v2(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { -; CHECK-LABEL: test

[PATCH] D86146: [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics

dmgreen added a comment. I mean, do we need upgrade code in llvm/lib/IR/AutoUpgrade.cpp for the new intrinsic forms? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86146/new/ https://reviews.llvm.org/D86146 ___ cfe-commits mailing list cfe-co

[PATCH] D86146: [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks. LGTM. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:473 def int_aarch64_neon_bfdot : AdvSIMD_Dot_Intrinsic; - def int_aarch64_neon_bfmmla : AdvSIMD_MatM

[PATCH] D87188: [InstCombine] Canonicalize SPF to abs intrinc

dmgreen added a comment. Thanks for the reproducer. I verified that it does indeed fail with this patch. It seems to be doing this as a knock-on effect: https://godbolt.org/z/Y4z3je, which does not verify: https://alive2.llvm.org/ce/z/PN7Rv5 ? Repository: rG LLVM Github Monorepo CHANGES SIN

[PATCH] D87188: [InstCombine] Canonicalize SPF to abs intrinc

dmgreen added a comment. Yeah. The reproducer seems to work OK with a patch something like this: diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 35c21a0..c517286 100644

[PATCH] D93022: [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

dmgreen added inline comments. Comment at: llvm/include/llvm/Support/ARMTargetParser.def:306 +ARM_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, + ARM::AEK_RAS) ARM_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, RA

[PATCH] D93022: [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

dmgreen added inline comments. Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:151 +AARCH64_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_RAS)) AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false

[PATCH] D93022: [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks. I think this LGTM now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93022/new/ https://reviews.llvm.org/D93022 _

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