dmgreen added inline comments.
================ Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:146 + case ARM::VMVNd: + case ARM::VMVNq: + // VMOV of 64-bit value between D registers (when condition = al) ---------------- lenary wrote: > dmgreen wrote: > > Perhaps add these, if they are safe: > > VBICd/q > > VBICi's, VORRi's > > VBIF/VBIT/VBSL/VBSP > > VCEQ/VCNE/etc? > > VDUP? VEXT? > > VMVN imm equivalents of VMOV's > > VREV's? > > VSHL's, VSHR's? > > I'm not sure if they will be very useful, but they are the kind of > > instructions that may come up in aes algorithms. > I'm very keen to avoid scope-creep on this patch, so I'm going to push back > on this comment. > > We know this list as given is safe (and have had internal confirmation). I've > sent a new email internally with your list of instructions, to find out of > they're safe too, but I'd like any answer to that to be part of a follow-up > patch rather than blocking this patch for yet longer. > > I believe what I have today is correct, even if the list is not optimal for > all expected AES code sequences. Yeah that sounds OK. So long as you address Simons comments and follow up with the instructions at a later date, this LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119720/new/ https://reviews.llvm.org/D119720 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
