[PATCH] D103873: [Clang][RISCV] Implement vsoxseg and vsuxseg.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103873/new/ https://reviews.llvm.org/D103873 ___

[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.

craig.topper added a comment. Does lowerRISCVVMachineInstrToMCInst in RISCVMCInstLower.cpp need to know to skip the policy op? Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:405 if (RISCVII::hasVLOp(TSFlags)) { const MachineOperand &VLOp = MI.getOperand(MI.ge

[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:25 +defvar TAIL_AGNOSTIC = 0; +defvar TAIL_UNDISTURBED = 1; Why are these the opposite polarity of what's in C? Repository: rG LLVM Github Monorepo CHANGES S

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added a comment. Why do they need to be disabled? Doesn’t the spec define them to truncate? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518 ___ cfe

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added a comment. In D106518#2895613 , @jacquesguan wrote: > In D106518#2895445 , @craig.topper > wrote: > >> Why do they need to be disabled? Doesn’t the spec define them to truncate? > > In the 1.0

[PATCH] D106277: [SVE] Remove the interface for getMaxVScale in favour of the IR attributes

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CodeGenFunction.cpp:504 VScale, VScale)); + } else if (getContext().getTargetInfo().hasFeature("sve")) { +CurFn->addFnAttr( Is the

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:40 + +static const StringRef AllStdExts = "mafdqlcbjtpvn"; + Make this `static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn";` Comment at: llvm/lib/Support

[PATCH] D106277: [SVE] Remove the interface for getMaxVScale in favour of the IR attributes

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CodeGenFunction.cpp:507 +CurFn->addFnAttr( +llvm::Attribute::getWithVScaleRangeArgs(getLLVMContext(), 0, 16)); } Thinking about this more, maybe these values should be returned from

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

craig.topper added a comment. I think this looks good to me. @luismarques or @jrtc27 any further feedback? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

craig.topper added inline comments. Comment at: llvm/test/MC/RISCV/rvv/aliases.s:86 +# NO-ALIAS: vfwredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0xc4] +vfwredusum.vs v8, v4, v20, v0.t jacquesguan wrote: > kito-cheng wrote: > > I guess you want to ver

[PATCH] D106210: [MS] Preserve base register %esi around movs[bwl]

craig.topper added a comment. In D106210#2899361 , @pengfei wrote: > Happened to see it. I thought Craig might miss it. Thanks @pengfei Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106210/new/ https://re

[PATCH] D106738: [RISCV] Use getNaturalPointeeTypeAlignment to get alignment for stores created for vector builtins.

craig.topper created this revision. craig.topper added reviewers: HsiangKai, evandro, khchen, arcbbb. Herald added subscribers: StephenFan, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jone

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

craig.topper added a comment. In D106701#2902544 , @dblaikie wrote: > In D106701#2901656 , @MaskRay wrote: > >> In D106701#2901639 , @efriedma >> wrote: >> >>> Can we hoo

[PATCH] D106738: [RISCV] Use getNaturalPointeeTypeAlignment to get alignment for stores created for vector builtins.

craig.topper updated this revision to Diff 361899. craig.topper added a comment. Also remove calls to getPointerElementType which will be removed eventually. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106738/new/ https://reviews.llvm.org/D106738

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

craig.topper added a comment. Does this work with LTO? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106701/new/ https://reviews.llvm.org/D106701 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:379 bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags); + // hasDummyMaskOp(TSFlags) == ture means it is a non-masked instruction. + // FIXME: hasDummyMaskOp() is the c

[PATCH] D107004: Turn off fp reassociation in IA intrinsic header files.

craig.topper added inline comments. Comment at: clang/lib/Headers/emmintrin.h:13 +/* Turn off reassociation for inrinsics, push state to restore at end. */ +#pragma float_control(push) inrinsics->intrinsics Comment at: clang/lib/Headers/xmmin

[PATCH] D107082: [X86][RFC] Enable `_Float16` type support on X86 following the psABI

craig.topper added a comment. I haven't had a chance to look at this patch in detail, but I wanted to ask if you considered doing what ARM and RISCV do for this. They pass the f16 in the lower bits on an f32 by only changing the ABI handling code in the backend. The type legalizer takes care of

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/maskedoff-undef.ll:3 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: --riscv-no-aliases < %s | FileCheck %s + frasercrmck wrote: > I don't think we'r

[PATCH] D121410: Have cpu-specific variants set 'tune-cpu' as an optimization hint

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/X86TargetParser.def:236 +CPU_SPECIFIC("core_i7_sse4_2", "nehalem", 'P', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt") +CPU_SPECIFIC("core_aes_pclmulqdq", "icelake-client", 'Q', "+cmov,+mmx

[PATCH] D121915: [RISCV] CLZ Instruction

craig.topper added a comment. These were intentionally not added because llvm has generic leading and trailing zero builtins. __builtin_clz and __builtin_ctz Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121915/new/ https://reviews.llvm.org/D12191

[PATCH] D121915: [RISCV] CLZ Instruction

craig.topper added a comment. Rethinking that. Since __builtin_clz is undefined for 0, I think we should have clang builtins, but we should use llvm.ctlz with false for the second argument as their implementation. See X86::BI__builtin_ia32_lzcnt_u32 for example. Repository: rG LLVM Github Mo

[PATCH] D122077: [InstCombine] Fold (ctpop(X) == 1) | (X == 0) into ctpop(X) < 2

craig.topper added inline comments. Comment at: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp:2613 + if (Value *V = foldOrOfCtpop(LHS, RHS, Builder)) +return V; Should we also handle the opposite version `ctpop(x) != 1 && x != 0`? =

[PATCH] D122077: [InstCombine] Fold (ctpop(X) == 1) | (X == 0) into ctpop(X) < 2

craig.topper added inline comments. Comment at: llvm/test/Transforms/InstCombine/icmp-or.ll:382 + ret i1 %5 +} + RKSimon wrote: > What about if the ctpop has multi uses? The ctpop isn't being changed. Does it matter if it has more uses? What is interesting is i

[PATCH] D122077: [InstCombine] Fold (ctpop(X) == 1) | (X == 0) into ctpop(X) < 2

craig.topper added inline comments. Comment at: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp:921 + if (IsAnd && + match(Cmp0, m_ICmp(Pred0, m_Intrinsic(m_Value(X)), + m_SpecificInt(1))) && Since the m_ICmp matches are the

[PATCH] D122104: [X86][regcall] Support passing / returning structures

craig.topper added inline comments. Comment at: clang/include/clang/CodeGen/CGFunctionInfo.h:744 + void setMaxVectorWidth(unsigned Width) { +MaxVectorWidth = llvm::Log2_32(Width) + 1; + } Are you assuming Width is a power of 2? Should we assert that?

[PATCH] D121915: [RISCV] CLZ Instruction

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:18910 +case RISCV::BI__builtin_riscv_clz_32: +case RISCV::BI__builtin_riscv_clz_64:{ + Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType()); Add a space bef

[PATCH] D121915: [RISCV] CLZ Instruction

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM though I think the title needs to be updated. Should be something like "[RISCV] Add clang builtins for CLZ instruction." Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

craig.topper added inline comments. Comment at: clang/lib/Headers/emmintrin.h:3476 +/// This intrinsic corresponds to the VMOVQ / MOVQ instruction +/// in 64 bits. /// craig.topper wrote: > 64 bits -> 64-bit mode 64 bits -> 64-bit CHANGES SINCE LAST ACTION

[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

craig.topper added a comment. The intrinsic interface doesn't care about 0https://reviews.llvm.org/D124186/new/ https://reviews.llvm.org/D124186 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:74 +// zbkb extension +TARGET_BUILTIN(__builtin_riscv_brev8, "ZiZi", "nc", "zbkb") Capital Z Comment at: clang/lib/Basic/Targets/RISCV.cpp:198 +

[PATCH] D110869: [X86] Implement -fzero-call-used-regs option

craig.topper added a comment. In D110869#3295906 , @void wrote: > In D110869#3295578 , > @nickdesaulniers wrote: > >> In D110869#3295559 , @void wrote: >> >>> Weird. We g

[PATCH] D110869: [X86] Implement -fzero-call-used-regs option

craig.topper added a comment. In D110869#3296031 , @void wrote: > In D110869#3295912 , @craig.topper > wrote: > >> In D110869#3295906 , @void wrote: >> >>> In D110869#329

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4503 case Intrinsic::riscv_vslide1down_mask: { // We need to special case these when the scalar is larger than XLen. unsigned NumOps = Op.getNumOperands(); Ar

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555 +def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add +X10_PD, X12_PD, X14_PD, X16_PD, Jim wrote: > Is

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

craig.topper added a comment. LGTM Note, I don't think vslidedown needs a tail policy, but vslideup does. But probably not worth making them different. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117681/new/ https://reviews.llvm.org/D117681 __

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:80 +// Zknd extension +TARGET_BUILTIN(__builtin_riscv_aes32dsi, "ZiZiZiUc", "nc", "zknd") +TARGET_BUILTIN(__builtin_riscv_aes32dsmi, "ZiZiZiUc", "nc", "zknd") Uc -> IUc T

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:181 + // The nomask intrinsic IR have the passthru operand. + bit HasNoMaskPolicy = false; + Should this be `HasNoMaskPassThru` rather than `Policy`? Co

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

craig.topper added a comment. LGTM other than what I think is an unnecessary include. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:15 #include "RISCVISelLowering.h" +#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVMatInt.h" This

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. In D93298#3326230 , @asb wrote: > I think all my comments have been addressed. @craig.topper - are you happy > your RegInfo question is addressed? I'm happy. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

craig.topper added a comment. The "B extension" terminology no longer exists. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:29 +TARGET_BUILTIN(__builtin_riscv_cpopw_64, "WiWi", "nc", "zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb") +TARGET_BUI

[PATCH] D124551: [Driver] Add f16 support to -mrecip parsing.

craig.topper created this revision. craig.topper added reviewers: spatel, efriedma, RKSimon. Herald added a subscriber: StephenFan. Herald added a project: All. craig.topper requested review of this revision. Herald added a subscriber: MaskRay. Herald added a project: clang. This is a followup to

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

craig.topper added a comment. I'm not opposed to this patch, but here's some additional info I think this is failing because we hit this code in CGExprScalar.cpp. Where SrcTy and DstTy are both i16 when using the conversion intrinsics. // Ignore conversions like int -> uint. if (SrcTy == Ds

[PATCH] D124551: [Driver] Add f16 support to -mrecip parsing.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGbd30d4be2354: [Driver] Add f16 support to -mrecip parsing. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACT

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124509/new/ https://reviews.llvm.org/D124509 ___

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM, but please fix the title to not use "B extension" since the "B extension" was never ratified. Only Zba, Zbb, Zbc, Zbs were ratified and there will never be a B. Repository:

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

craig.topper added inline comments. Comment at: clang/test/Driver/riscv-arch.c:541 +// RUN: FileCheck -check-prefix=RV32-ZVE32F-GOOD %s +// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f" Do we have tests for zve64*? Repository: rG LLVM Github Monorepo CHANG

[PATCH] D124916: [X86] Fix uninitialized variable warnings in cetintrin.h reported by #55224

craig.topper added inline comments. Comment at: clang/lib/Headers/cetintrin.h:45 static __inline__ unsigned int __DEFAULT_FN_ATTRS _rdsspd_i32() { +#pragma clang diagnostic push The argument should also be `(void)`. Comment at: clang/lib/Hea

[PATCH] D124916: [X86] Fix uninitialized variable warnings in cetintrin.h reported by #55224

craig.topper added inline comments. Comment at: clang/lib/Headers/cetintrin.h:48 +#pragma clang diagnostic ignored "-Wuninitialized" unsigned int t; return __builtin_ia32_rdsspd(t); So if CET isn't enabled this intrinsic returns a random value instead of 0

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124611/new/ https://reviews.llvm.org/D124611 ___

[PATCH] D103313: [RISCV][Clang] Add support for Zmmul extension

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. Need to update RISCVTargetLowering::decomposeMulByConstant. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103313/new/ https://reviews.llvm.org/D103313 _

[PATCH] D129572: [X86] initial -mfunction-return=thunk-extern support

craig.topper accepted this revision. craig.topper added a comment. I also reviewed off-list and the X86 parts LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129572/new/ https://reviews.llvm.org/D129572 _

[PATCH] D103313: [RISCV][Clang] Add support for Zmmul extension

craig.topper accepted this revision. craig.topper added inline comments. This revision is now accepted and ready to land. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:80 +{"zmmul", RISCVExtensionVersion{0, 1}}, + If it is ratified, is the version really 0.

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper created this revision. craig.topper added reviewers: reames, asb, luismarques, arcbbb, frasercrmck, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper added inline comments. Comment at: clang/test/CodeGen/builtin_float_strictfp.c:3 // RUN: %clang_cc1 -no-opaque-pointers -emit-llvm -triple ppc64-be -ffp-exception-behavior=maytrap -o - %s | FileCheck %s --check-prefixes=CHECK,NOFP16 +// RUN: %clang_cc1 -no-opaque-

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:933 + if (!Subtarget.hasVInstructions()) +IsStrictFPEnabled = true; + Setting this to true disables some code in SelectionDAGISel.cpp that make ISD::STRICT_* nodes c

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:879 + // intrinsic: (passthru0, passthru1, ..., ptr, vl) + SmallVector Operands; + for (unsigned I = 0; I < NF; ++I) Why 12? NF is at most 8 right? And then 2

[PATCH] D123498: [clang] Adding Platform/Architecture Specific Resource Header Installation Targets

craig.topper added inline comments. Comment at: clang/lib/Headers/CMakeLists.txt:421 install( FILES ${ppc_wrapper_files} There appear to be two installs of ppc_wrapper_files with different components. Is that intentional? Repository: rG LLVM Github Mon

[PATCH] D123498: [clang] Adding Platform/Architecture Specific Resource Header Installation Targets

craig.topper added inline comments. Comment at: clang/lib/Headers/CMakeLists.txt:421 install( FILES ${ppc_wrapper_files} qiongsiwu1 wrote: > craig.topper wrote: > > There appear to be two installs of ppc_wrapper_files with different > > components. Is that

[PATCH] D125491: [RISCV] Add extra space into error message about unsupported extension version.

craig.topper created this revision. craig.topper added reviewers: kito-cheng, khchen, arcbbb, asb, luismarques, jrtc27. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, br

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125323/new/ https://reviews.llvm.org/D125323 ___

[PATCH] D125491: [RISCV] Add extra space into error message about unsupported extension version.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG232c00ba5bd1: [RISCV] Add extra space into error message about unsupported extension version. (authored by craig.topper). Changed prior to commit:

[PATCH] D125789: FIX the assembly format of the x86 backend to make both clang and gcc happy

craig.topper added a comment. Is it gcc that needs a fix or binutils? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125789/new/ https://reviews.llvm.org/D125789 ___ cfe-commits mailing list cfe-commits@l

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

craig.topper added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:346 + getSuffixStr(BasicType Type, int Log2LMUL, + const llvm::ArrayRef &PrototypeDescriptors); }; Drop the `const` and the reference Repository:

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1511 +__extension__ extern __inline +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +unsigned long vread_csr(enum RVV_CSR csr) { Do we need __gnu_inline

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1512 +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +unsigned long vread_csr(enum RVV_CSR csr) { + unsigned long rv = 0; pcwang-thead wrote: > craig.t

[PATCH] D123498: [clang] Adding Platform/Architecture Specific Resource Header Installation Targets

craig.topper added inline comments. Comment at: clang/lib/Headers/CMakeLists.txt:421 install( FILES ${ppc_wrapper_files} qiongsiwu1 wrote: > craig.topper wrote: > > qiongsiwu1 wrote: > > > craig.topper wrote: > > > > There appear to be two installs of ppc_w

[PATCH] D123498: [clang] Adding Platform/Architecture Specific Resource Header Installation Targets

craig.topper added inline comments. Comment at: clang/lib/Headers/CMakeLists.txt:537 + FILES ${openmp_wrapper_files} + DESTINATION ${header_install_dir} + EXCLUDE_FROM_ALL Should this be ${header_install_dir}/openmp_wrappers Repository: rG LLVM Github Mono

[PATCH] D126002: [clang] Fixing arm-common, windows only and openmp header install targets

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126002/new/ https://reviews.llvm.org/D126002 ___

[PATCH] D126137: [X86] Add support for `-mharden-sls=all`

craig.topper added a comment. What is #1633 in the description? Can you make a link? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126137/new/ https://reviews.llvm.org/D126137 ___ cfe-commits mailing lis

[PATCH] D126137: [X86] Add support for `-mharden-sls=all`

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86AsmPrinter.cpp:341 + MCInst TmpInst; + TmpInst.setOpcode(X86::INT3); + AsmPrinter::emitBasicBlockEnd(MBB); Why is TmpInst created unconditionally and not in the if? Repository: rG LLVM

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16200 SDValue Hi; - if (VA.getLocReg() == RISCV::X17) { // Second half of f64 is passed on the stack. This code has been rewritten recently. Please rebase Repos

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper abandoned this revision. craig.topper added a comment. I don't think so. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63638/new/ https://reviews.llvm.org/D63638 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://l

[PATCH] D66669: [X86] Remove what little support we had for MPX

craig.topper updated this revision to Diff 217056. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Add to clang and llvm release notes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D9/new/ htt

[PATCH] D66862: Make lround builtin constexpr (and others)

craig.topper added a comment. What if the input is nan or infinity or out of range. The spec says an implementation defined value is returned. But we've deferred to whatever library we're compiled with. Which makes our implementation defined behavior outside of clang's control and it now depend

[PATCH] D66862: Make lround builtin constexpr (and others)

craig.topper added inline comments. Comment at: clang/lib/AST/ExprConstant.cpp:9616 +return EvaluateFloat(E->getArg(0), Val, Info) && + Success(lround(Val.convertToDouble()), E); + } zoecarver wrote: > lebedev.ri wrote: > > zoecarver wrote: > > > r

[PATCH] D66862: Make lround builtin constexpr (and others)

craig.topper added inline comments. Comment at: clang/lib/AST/ExprConstant.cpp:9620 + +if(!EvaluateFloat(E->getArg(0), FPVal, Info)) return false; +APFloat::opStatus status = Space after if Comment at: clang/lib/AST/ExprConstant.cpp:962

[PATCH] D66983: [WebAssembly] Add wasm-specific vector shuffle builtin and intrinsic

craig.topper added a comment. x86 is aggressive about optimizing shuffles no matter where they came from. FWIW, InstCombine has a general rule that its not supposed to create a shuffle mask that didn't already exist in the IR except for special things like identity masks that would allow the sh

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper added a comment. In D64672#1653847 , @RKSimon wrote: > Please can you extend the test coverage to cover more vector sizes and cpu > target features, not just avx512, and also add x86_64-scei-ps4 triple tests. > Maybe 32-bit tests as well?

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper updated this revision to Diff 218284. craig.topper added a comment. Add more tests. Clarify which platforms are affected in LangOptions.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64672/new/ https://reviews.llvm.org/D64672 Files:

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper added a comment. In D64672#1654687 , @RKSimon wrote: > Tests look great - please can you pre-commit them and update the patch to > show the diff? Also, maybe call the test file x86-vec-i128.c and add a > comment in the file describing PR4260

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper updated this revision to Diff 218506. craig.topper added a comment. Change test name and adjust to the changes I think @rksimon was asking for. I haven't commited the test yet. I'd like to verify that the before version of the test is how you would like it pre-committed CHANGES SI

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper closed this revision. craig.topper added a comment. Committed in r371169, but I forgot the Differential Revision line CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64672/new/ https://reviews.llvm.org/D64672 ___ cfe-commits mail

[PATCH] D35996: [X86][AVX] Ensure vector non-temporal load/store intrinsics force pointer alignment (PR33830)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D35996 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D35449: [X86] Implement __builtin_cpu_is

craig.topper added a comment. @erichkeane are you ok with this code for now? I think validateCPUIs gives you what you need at least for Sema support for target attribute. You'll probably need to refactor the CG code to make your ifunc resolver. But I think you need to do that for the existing f

[PATCH] D36336: [X86] Add support for __builtin_cpu_init

craig.topper created this revision. This adds __builtin_cpu_init which will emit a call to __cpu_indicator_init in libgcc or compiler-rt. This is needed to support __builtin_cpu_supports/__builtin_cpu_is in an ifunc resolver. https://reviews.llvm.org/D36336 Files: include/clang/Basic/Built

[PATCH] D36362: [X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang part

craig.topper created this revision. On older processors this instruction encoding is treated as a NOP. MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics w

[PATCH] D36362: [X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang part

craig.topper updated this revision to Diff 109896. craig.topper added a comment. Add test case https://reviews.llvm.org/D36362 Files: include/clang/Basic/BuiltinsX86.def test/CodeGen/pause.c Index: test/CodeGen/pause.c === --

[PATCH] D35449: [X86] Implement __builtin_cpu_is

craig.topper added a comment. Ping https://reviews.llvm.org/D35449 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D36530: [Parse] Document PrintStats, SkipFunctionBodies

craig.topper resigned from this revision. craig.topper added a comment. Guessing I'm only on here because I did the bulk of the 0->nullptr changes to clang a few years back. https://reviews.llvm.org/D36530 ___ cfe-commits mailing list cfe-commits@l

[PATCH] D36707: [CodeGen]Refactor CpuSupports/CPUIs Builtin Code Gen to better work with "target" implementation

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D36707 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D36336: [X86] Add support for __builtin_cpu_init

craig.topper added a comment. Ping https://reviews.llvm.org/D36336 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D72010: [CodeGen] Use CreateFNeg in buildFMulAdd

craig.topper created this revision. craig.topper added reviewers: cameron.mcinally, rjmccall, efriedma, rsmith. We have an fneg instruction now and should use it instead of the fsub -0.0 idiom. Looks like we had no test that showed that we handled the negation cases here so I've added new tests.

[PATCH] D72010: [CodeGen] Use CreateFNeg in buildFMulAdd

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGExprScalar.cpp:3350 +MulOp0 = Builder.CreateFNeg(MulOp0, "neg"); + if (negAdd) +Addend = Builder.CreateFNeg(Addend, "neg"); I removed the '

[PATCH] D72012: [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj

craig.topper created this revision. craig.topper added reviewers: spatel, efriedma, rjmccall, cameron.mcinally. This replaces the fsub -0.0 idiom with an fneg instruction. We didn't see to have a test that showed the current codegen. Just some tests for constant folding and a test that was only

[PATCH] D72012: [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj

This revision was automatically updated to reflect the committed changes. Closed by commit rG70f8dd4cf604: [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj (authored by craig.topper). Herald added a project: clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://r

[PATCH] D72010: [CodeGen] Use CreateFNeg in buildFMulAdd

This revision was automatically updated to reflect the committed changes. Closed by commit rG8b23b2bbd962: [CodeGen] Use CreateFNeg in buildFMulAdd (authored by craig.topper). Herald added a project: clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.or

[PATCH] D72028: [CodeGen] Emit conj/conjf/confjl libcalls as fneg instructions if possible.

craig.topper created this revision. craig.topper added reviewers: spatel, efriedma, rjmccall. Herald added a project: clang. We already recognize the __builtin versions of these, might as well recognize the libcall version. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D72028

[PATCH] D72028: [CodeGen] Emit conj/conjf/confjl libcalls as fneg instructions if possible.

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: clang/test/CodeGen/complex-libcalls.c:115-118 +// NO__ERRNO-NOT: .conj +// NO__ERRNO-NOT: @conj +// HAS_ERRNO-NOT: .conj +// HAS_ERRNO-NOT: @conj spatel wrote: > Could

[PATCH] D72028: [CodeGen] Emit conj/conjf/confjl libcalls as fneg instructions if possible.

This revision was automatically updated to reflect the committed changes. Closed by commit rG5e5a1d279096: [CodeGen] Emit conj/conjf/confjl libcalls as fneg instructions if possible. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llv

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