[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16200
   SDValue Hi;
-  if (VA.getLocReg() == RISCV::X17) {
     // Second half of f64 is passed on the stack.
----------------
This code has been rewritten recently. Please rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401

_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits