[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:2262 + /// Return true if the given vector types are lax-compatible RVV vector types, + /// false otherwise. + bool areLaxCompatibleRVVTypes(QualType FirstType, QualType SecondType);

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4259197 , @erichkeane wrote: > has this had an RFC btw? I don't believe I've seen one, and this looks like > we probably need one. It has not had an RFC. It's almost a direct copy of AArch64's implementation,

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4258856 , @erichkeane wrote: > So I don't see any handling of the dependent version of this, we probably > need tests for those at minimum. Does SVE handle the dependent version? Repository: rG LLVM Github M

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper added a comment. What if we attached the domain as a separate RISC-V specific metadata and didn't change the nontemporal format? If optimizations drop the RISC-V specific part it would still be nontemporal, but get the default domain? Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:2262 + /// Return true if the given vector types are lax-compatible RVV vector types, + /// false otherwise. + bool areLaxCompatibleRVVTypes(QualType FirstType, QualType SecondType);

[PATCH] D147935: [RISCV] Add SiFive extension support

craig.topper added a comment. Is there a different patch with the .td for these intrinsics? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147935/new/ https://reviews.llvm.org/D147935 ___ cfe-commits mail

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

craig.topper added a comment. What is the interaction between this and the -m32 and -m64 options? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148124/new/ https://reviews.llvm.org/D148124 ___ cfe-commit

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp:12 + +template struct S { T var; }; + @erichkeane does this cover the dependent case or were you looking for something else? Here are on the only mentions of templ

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:2262 + /// Return true if the given vector types are lax-compatible RISC-V vector + /// types as defined by -flax-vector-conversions=, false otherwise. + bool areLaxCompatibleRVVTypes(QualType

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp:12 + +template struct S { T var; }; + erichkeane wrote: > craig.topper wrote: > > @erichkeane does this cover the dependent case or were you looking for > > somethi

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp:12 + +template struct S { T var; }; + aaron.ballman wrote: > erichkeane wrote: > > craig.topper wrote: > > > erichkeane wrote: > > > > craig.topper wrote: > > > > >

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c:19 +typedef signed short v8ss __attribute__((vector_size(16))); +typedef signed char v16sc __attribute__((vector_size(16))); +v4si v4si1, v4si2; What abou

[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

craig.topper added a comment. I'm not sure I want to suggest this, but could we disable the emission of the relocations that can be GP relaxed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148034/new/ https://reviews.llvm.org/D148034 ___

[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

craig.topper added a comment. In D148034#4262938 , @jrtc27 wrote: > In D148034#4262934 , @craig.topper > wrote: > >> I'm not sure I want to suggest this, but could we disable the emission of >> the relocations t

[PATCH] D147935: [RISCV] Add SiFive extension support

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147935/new/ https://reviews.llvm.org/D147935 ___

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp:12 + +template struct S { T var; }; + aaron.ballman wrote: > craig.topper wrote: > > aaron.ballman wrote: > > > erichkeane wrote: > > > > craig.topper wrote: > > > >

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148124/new/ https://reviews.llvm.org/D148124 ___

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp:12 + +template struct S { T var; }; + erichkeane wrote: > craig.topper wrote: > > aaron.ballman wrote: > > > craig.topper wrote: > > > > aaron.ballman wrote: > > > >

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

craig.topper added a comment. We need SemaChecking.cpp code to check the range of the constant arguments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 ___ cf

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2422 + // Log2LMUL to zero. Otherwise the RISCVVEmitter will expand + // lots of redunant intrinsic but have same names. + let Log2LMUL = [0] in r

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c:19 +typedef signed short v8ss __attribute__((vector_size(16))); +typedef signed char v16sc __attribute__((vector_size(16))); +v4si v4si1, v4si2; BeMg wrot

[PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

craig.topper created this revision. craig.topper added a reviewer: MaskRay. Herald added subscribers: ThomasRaoux, kbarton, hiraditya, nemanjai. Herald added a project: All. craig.topper requested review of this revision. Herald added a reviewer: zuban32. Herald added subscribers: lldb-commits, cfe

[PATCH] D151145: Add disabled unittest reproducing TextProto formatting issue.

craig.topper added a comment. I don't think I'm the right reviewer for this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151145/new/ https://reviews.llvm.org/D151145 ___ cfe-commits mailing list cfe-co

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

craig.topper added a comment. Please split clang and llvm codegen into separate patches. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150253/new/ https://reviews.llvm.org/D150253 ___ cfe-commits mailing

[PATCH] D150114: [Headers][doc] Add "add/sub/mul" intrinsic descriptions to avx2intrin.h

craig.topper added inline comments. Comment at: clang/lib/Headers/avx2intrin.h:456 +/// j := i*128 +/// result[j+31:j] := __a[j+63:j+32] - __a[j+31:j] +/// result[j+63:j+32] := __a[j+127:j+96] - __a[j+95:j+64] Intel intrinsics guide says ``` dst[31:0] := a

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1018 +if (VT.getVectorElementType() == MVT::f16 && +!Subtarget.hasVInstructionsF16()) { This needs to be below `By default everything must be expande

[PATCH] D150670: [WebAssembly] Disable generation of fshl/fshr for rotates

craig.topper added a comment. In D150670#4367736 , @pmatos wrote: > In D150670#4352094 , @craig.topper > wrote: > >>> Preventing the simplification means adding target specific code in >>> instcombine which seem

[PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

This revision was automatically updated to reflect the committed changes. Closed by commit rG6006d43e2d7d: LLVM_FALLTHROUGH => [[fallthrough]]. NFC (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150996/new/ https://reviews

[PATCH] D151397: [3/N][RISCV] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2131 +} + Extra blank line Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c:16 // -vint8mf8_t test_

[PATCH] D151397: [3/N][RISCV] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:1365 defm vaaddu : RISCVSaturatingBinaryAAX; - defm vaadd : RISCVSaturatingBinaryAAX; - defm vaadd_rm : RISCVSaturatingBinaryAAXRoundingMode; + defm vaadd : RISCVSaturatingBinaryAAXRound

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162 + bool hasVInstructionsF16Mininal() const { +return HasStdExtZvfhmin || HasStdExtZvfh; + } michaelmaitland wrote: > michaelmaitland wrote: > > jacquesguan wrote: > >

[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150926/new/ https://reviews.llvm.org/D150926 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162 + bool hasVInstructionsF16Mininal() const { +return HasStdExtZvfhmin || HasStdExtZvfh; + } jacquesguan wrote: > craig.topper wrote: > > michaelmaitland wrote: > > > m

[PATCH] D151730: [WIP][RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-func-attr-target.c:1 +// REQUIRES: riscv-registered-target +// RUN: %clang -target riscv64 -march=rv64g -S %s -o - | FileCheck %s No test for tune=? Repository: rG LLVM Github Mono

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. We need to support reinterpret intrinsics so that we can load/store bf16 values. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.o

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:200 + bool HasZvfhminOrZvfh = TI.hasFeature("experimental-zvfhmin") || + TI.hasFeature("experimental-zvfh"); You can reuse `HasZvfh` here Reposi

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper added a comment. In D150253#4382857 , @jacquesguan wrote: > In D150253#4381435 , @craig.topper > wrote: > >> We need to support reinterpret intrinsics so that we can load/store bf16 >> values. > >

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150253/new/ https://reviews.llvm.org/D150253 ___

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper added a comment. Do we need to enable these intrinsics for Zvfhmin? vfloat16mf4_t __riscv_vle16_v_f16mf4 (const float16_t *base, size_t vl); vfloat16mf2_t __riscv_vle16_v_f16mf2 (const float16_t *base, size_t vl); vfloat16m1_t __riscv_vle16_v_f16m1 (const float16_t *base, size_

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper reopened this revision. craig.topper added a comment. This revision is now accepted and ready to land. The backend patch must go before the clang patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150253/new/ https://reviews.llvm.org

[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150926/new/ https://reviews.llvm.org/D150926 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D151397: [3/N][RISCV] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2079 +[{ +enum RVV_VXRM { + VXRM_RNU = 0, enum name needs `__` prefix Comment at: clang/include/clang/Basic/riscv_vector.td:2080 +enum RVV_VXRM { + VXRM

[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

craig.topper added a comment. Doesn't this make codegen worse on when those extensions aren't supported? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151867/new/ https://reviews.llvm.org/D151867 ___ cfe

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2219 + def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">; + let RequiredFeatures = ["ZvfhminOrZvfh"] in +def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f">

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86Operand.h:386 return false; +if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef) + return true; Wouldn't this allow "symbol + %eax" to pick the 64-bit instruction

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:1781 + // value at this time. + BaseReg = BaseReg ? BaseReg : 0; Operands.push_back(X86Operand::CreateMem( This sets BaseReg to 0 if its already 0? Repository:

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86Operand.h:386 return false; +if (getMemBaseReg() == X86::NoRegister) + return true; Now we're not checking the index register if there is no base register? Reposito

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

craig.topper added a comment. I still think replacing the `1` with a valid register for the mode is the better fix. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151863/new/ https://reviews.llvm.org/D151863 ___

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

craig.topper added a comment. In D151863#4390172 , @akshaykhadse wrote: > In D151863#4390132 , @craig.topper > wrote: > >> I still think replacing the `1` with a valid register for the mode is the >> better fix

[PATCH] D152023: [UBSan] Consider zero input to __builtin_clz/ctz to be undefined independent of the target.

craig.topper created this revision. craig.topper added reviewers: efriedma, nikic, vsk. Herald added a subscriber: StephenFan. Herald added a project: All. craig.topper requested review of this revision. Herald added a project: clang. Previously we checked isCLZForZeroUndef and only added UBSan ch

[PATCH] D152023: [UBSan] Consider zero input to __builtin_clz/ctz to be undefined independent of the target.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG18ccca4da8de: [UBSan] Consider zero input to __builtin_clz/ctz to be undefined independent of… (authored by craig.topper). Repository: rG LLVM Git

[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

craig.topper added a comment. Description says "XTHeadBs" instead of "XTHeadBb" Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143439/new/ https://reviews.llvm.org/D143439 ___ cfe-commits mailing list cfe

[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:318 +if (Subtarget.is64Bit()) + setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom); + } without these two lines to promote i32, I suppose we

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

craig.topper added a comment. Are you going to do f32, f64, and i64 as well? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143657/new/ https://reviews.llvm.org/D143657 ___ cfe-commits mailing list cfe-co

[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:318 +if (Subtarget.is64Bit()) + setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom); + } philipp.tomsich wrote: > craig.topper wrote: > > wit

[PATCH] D143665: [Clang][RISCV] Guard vector int64, float32, float64 with semantic analysis

craig.topper added inline comments. Comment at: clang/include/clang/AST/Type.h:7209 +inline bool Type::isVectorFloat32Type() const { +#define RVV_TYPE(Name, Id, SingletonId) false || This function is RVV specific so it's name is misleading. It's also identical

[PATCH] D137309: [clang] Added Swift support for RISCV

craig.topper added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10555 namespace { -class RISCVABIInfo : public DefaultABIInfo { +class RISCVABIInfo : public SwiftABIInfo { private: SwiftABIInfo doesn't inherit from ABIInfo and hasn't since Augu

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

craig.topper added inline comments. Comment at: clang/lib/Sema/Sema.cpp:2052 + Diag(Loc, diag::err_riscv_type_requires_extension, FD) + << Ty << "experimental-zvfh"; +} experimental- is an internal naming scheme. "experimental-" is not used in

[PATCH] D143665: [Clang][RISCV] Guard vector int64, float32, float64 with semantic analysis

craig.topper added inline comments. Comment at: clang/lib/Sema/Sema.cpp:2049 -if (Ty->isVectorFloat16Type() && -!Context.getTargetInfo().hasVectorFloat16Support()) { +if ((Ty->isVectorInt64Type() && + !Context.getTargetInfo().hasVectorInt64Support()) ||

[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143439/new/ https://reviews.llvm.org/D143439 ___

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143657/new/ https://reviews.llvm.org/D143657 ___

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:326 +unsigned Val; +bool IsRV64; + }; Is this IsRV64 field used? Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:331 +

[PATCH] D143665: [Clang][RISCV] Guard vector int64, float32, float64 with semantic analysis

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143665/new/ https://reviews.llvm.org/D143665 ___

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:135 +def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm5:$index), + "cm.jt", "$index">{ + bits<5> index; Indent 1 more space Repository: rG LLVM

[PATCH] D144147: [Clang][RISCV] Sort test cases into its mnemonics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D144147/new/ https://reviews.llvm.org/D144147 ___

[PATCH] D144288: [RISCV] Add missing plumbing and tests for zfa

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:853 // Note: The table needs to be sorted by name. static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"v"}, {ImpliedExtsV}}, I think zfa should imply F here? Repository:

[PATCH] D144288: [RISCV] Add missing plumbing and tests for zfa

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D144288/new/ https://reviews.llvm.org/D144288 ___ cfe-commits mailing list c

[PATCH] D144447: [Clang] Teach buildFMulAdd to peek through fneg to find fmul.

craig.topper created this revision. craig.topper added reviewers: efriedma, aaron.ballman, andrew.w.kaylor, kpn, spatel, uweigand. Herald added a subscriber: StephenFan. Herald added a project: All. craig.topper requested review of this revision. Herald added a project: clang. Allows us to handle

[PATCH] D144447: [Clang] Teach buildFMulAdd to peek through fneg to find fmul.

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGExprScalar.cpp:3738 - assert(!(negMul && negAdd) && "Only one of negMul and negAdd should be set."); - Value *MulOp0 = MulOp->getOperand(0); kpn wrote: > If I'm reading this right it looks l

[PATCH] D144613: [RISCV] Properly diagnose mixing RVV scalable vectors with GNU vectors.

craig.topper created this revision. craig.topper added reviewers: kito-cheng, reames, frasercrmck, eopXD, rogfer01, c-rhodes. Herald added subscribers: luke, VincentWu, ctetreau, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D144613: [RISCV] Properly diagnose mixing RVV scalable vectors with GNU vectors.

This revision was automatically updated to reflect the committed changes. Closed by commit rGdbf149c91b7b: [RISCV] Properly diagnose mixing RVV scalable vectors with GNU vectors. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D144613?vs=499711&id=499882#toc Repos

[PATCH] D144447: [Clang] Teach buildFMulAdd to peek through fneg to find fmul.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG83cd4bea015f: [Clang] Teach buildFMulAdd to peek through fneg to find fmul. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANG

[PATCH] D144696: [RISCV][NFC] Package version number information using RISCVExtensionVersion.

craig.topper added a comment. You outline your full plan and why you want to do this. We need to see the bigger picture. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D144696/new/ https://reviews.llvm.org/D144696 __

[PATCH] D144696: [RISCV][NFC] Package version number information using RISCVExtensionVersion.

craig.topper added a comment. In D144696#4149545 , @ym1813382441 wrote: > F26630797: Screenshot from 2023-02-24 15-54-21.png > I meant what extensions are you planning to support multiple versions for and why? How

[PATCH] D144696: [RISCV][NFC] Package version number information using RISCVExtensionVersion.

craig.topper added a comment. How much of the existing vector code in the backend including tablegen can be reused for 0.71? How much of the intrinsic interface can be used? If we’re talking about completely duplicating everything it is very unlikely we can accept it. RISCVGenDAGISel.inc, for e

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. The instructions need a DecoderNamespace to separate them from c.fsdsp. See D149891 for how I've done it for Zcmt. Repository: rG LL

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:1418 + def int_riscv_vreinterpret_v +: DefaultAttrsIntrinsic<[llvm_anyvector_ty], Do we need an intrinsic? m1 -> mask is bitcast m1 vscale type to and a llvm.ex

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:1418 + def int_riscv_vreinterpret_v +: DefaultAttrsIntrinsic<[llvm_anyvector_ty], craig.topper wrote: > Do we need an intrinsic? > > m1 -> mask is bitcast m1 vsca

[PATCH] D150021: [RISCV] Make zve32f imply F and zve64d imply D.

craig.topper created this revision. craig.topper added reviewers: asb, kito-cheng, reames, frasercrmck, rogfer01. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbe

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:3387 + } + case RISCV::CM_POPRET: + case RISCV::CM_POPRETZ: Why is this needed? Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinte

[PATCH] D150021: [RISCV] Make zve32f imply F and zve64d imply D.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG728b8a139804: [RISCV] Make zve32f imply F and zve64d imply D. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D15002

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:3164 } - return false; Drop this change Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:650 +LLVM_DEBUG( +

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D132819/new/ https://reviews.llvm.org/D132819 ___

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2042 + + SmallVector Operands; + if (ResultType->isIntOrIntVectorTy(1)) { Don't use SmallVector for a fixed number of items. You can use a plain array. R

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:112 + // Note: c >= 1 since the smallest VLUpperBound is 512 / 8 = 8, and the + // largest division performed on VLUpperBound is in MF8 case with division + // by 8. Therefore, there is

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

craig.topper added a comment. Don’t you need to make f16 vectors legal types in the backend? And you need to disable intrinsics for instructions that aren’t supported by Zfhmin. Like f16 vector fadd And you also need to make the backend only allow f16 vector operations that are supported with

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2042 + + SmallVector Operands; + if (ResultType->isIntOrIntVectorTy(1)) { This SmallVector is unused Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D150490: Enable frame pointer for all non-leaf functions on riscv64 Android

craig.topper added a comment. Is there more context on why Android enables the frame pointer? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150490/new/ https://reviews.llvm.org/D150490 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[PATCH] D150490: Enable frame pointer for all non-leaf functions on riscv64 Android

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:530 + Triple.isAArch64() || Triple.isPS() || Triple.isVE() || + (Triple.isAndroid() && (Triple.getArch() == llvm::Triple::riscv64))); if (NoOmitFP || must

[PATCH] D150490: Enable frame pointer for all non-leaf functions on riscv64 Android

craig.topper added a comment. In D150490#4343145 , @enh wrote: > In D150490#4343128 , @hiraditya > wrote: > >>> Is there more context on why Android enables the frame pointer? >> >> From what i gathered, this is

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

craig.topper added a subscriber: michaelmaitland. craig.topper added a comment. In D150253#4341545 , @jacquesguan wrote: > To enable specific EEW for specific insturction in instruction selection, I > will create some parent revisions. Here is the first

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149642/new/ https://reviews.llvm.org/D149642 ___

[PATCH] D150114: [Headers][doc] Add "add/sub/mul" intrinsic descriptions to avx2intrin.h

craig.topper added inline comments. Comment at: clang/lib/Headers/avx2intrin.h:156 +///A 256-bit vector containing one of the source operands. +/// \returns A 256-bit vector containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 Why do some ret

[PATCH] D150690: [RISCV] Use IRBuilder::CreateInsertVector/CreateExtractVector to simplify code. NFC

craig.topper created this revision. craig.topper added reviewers: eopXD, kito-cheng. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jone

[PATCH] D150690: [RISCV] Use IRBuilder::CreateInsertVector/CreateExtractVector to simplify code. NFC

craig.topper updated this revision to Diff 522690. craig.topper added a comment. Update more intrinsics Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150690/new/ https://reviews.llvm.org/D150690 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D150646: [clang][X86] Add __cpuidex function to cpuid.h

craig.topper added a comment. For MSVC compatibility this was already implemented as a builtin for intrin.h in https://reviews.llvm.org/D121653 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150646/new/ https://reviews.llvm.org/D150646 ___

[PATCH] D150646: [clang][X86] Add __cpuidex function to cpuid.h

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM I find it a little odd that we have if you include cpuid.h you get the gcc interface for __cpuid and the MSVC interface for __cpuidex. But gcc did it first so I guess we shou

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGCall.cpp:3070 + + llvm::Value *LoadedStructValue = CreateCoercedLoad(Ptr, STy, *this); + eopXD wrote: > craig.topper wrote: > > What are we loading here? > > > > Is there a test for thi

[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150777/new/ https://reviews.llvm.org/D150777 ___

[PATCH] D150690: [RISCV] Use IRBuilder::CreateInsertVector/CreateExtractVector to simplify code. NFC

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG77f38e1325a2: [RISCV] Use IRBuilder::CreateInsertVector/CreateExtractVector to simplify code. (authored by craig.topper). Repository: rG LLVM Git

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