[PATCH] D155220: [IRGen] Remove 'Sve' from the name of some IR names that are shared with RISC-V now.

craig.topper created this revision. craig.topper added reviewers: joechrisellis, bsmith, c-rhodes, sdesmalen. Herald added subscribers: VincentWu, vkmr, luismarques, sameer.abuasal, s.egerton, Jim, rogfer01, shiva0217, kito-cheng, simoncook, arichardson. Herald added a project: All. craig.topper r

[PATCH] D155222: [RISCV][AArch64][IRGen] Add scalable->fixed as a special case in CreateCoercedStore.

craig.topper created this revision. craig.topper added reviewers: bsmith, sdesmalen, c-rhodes, joechrisellis. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbe

[PATCH] D155146: Add SHA512 instructions.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:243 + "Support SHA512 instructions", + [FeatureAVX]>; // Processor supports CET SHSTK - Control-Flow Enforcement Technology --

[PATCH] D154596: [RISCV] Fix required features checking with empty string

craig.topper added a comment. This seems reasonable to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154596/new/ https://reviews.llvm.org/D154596 ___ cfe-commits mailing list cfe-commits@lists.llvm.o

[PATCH] D155145: Add AVX-VNNI-INT16 instructions.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll:3 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx2,+avxvnniint16 | FileCheck %s --check-prefixes=X64 +; RUN: llc < %s -verify-m

[PATCH] D155145: Add AVX-VNNI-INT16 instructions.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8303 + def rr : I("int_x86_avx2_"#OpcodeStr#"_128") + VR128:$src1, VR128:$src2, VR128:$src3)))]>, This needs to be indented 1 character more so that it looks

[PATCH] D154596: [RISCV] Fix required features checking with empty string

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154596/new/ https://reviews.llvm.org/D154596 ___

[PATCH] D86310: [X86] Align i128 to 16 bytes in x86-64 datalayout

craig.topper added a comment. > @craig.topper Just to make sure, are you okay with me 'commandeering' this > change and updating it? Yes. Thanks for taking it on. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86310/new/ https://reviews.llvm.org/D86310

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154647/new/ https://reviews.llvm.org/D154647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D154616: [RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154616/new/ https://reviews.llvm.org/D154616 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D155326: [Clang][lld][RISCV] Passing 'mattr' to lld/llvmgold

craig.topper added a comment. -mattr is a different syntax than -march that users are used to. Why would we want to expose that? There was previously a proposal for doing this automatically https://reviews.llvm.org/D132843 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION htt

[PATCH] D155326: [Clang][lld][RISCV] Passing 'mattr' to lld/llvmgold

craig.topper added a comment. In D155326#4502097 , @dtcxzyw wrote: > In D155326#4501997 , @jrtc27 wrote: > >> Why do you believe this is better than encoding it in the module's IR like >> the ABI? > > > > - There

[PATCH] D154616: [RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.

craig.topper updated this revision to Diff 540651. craig.topper added a comment. Rebase. I'll commit tomorrow. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154616/new/ https://reviews.llvm.org/D154616 Files: clang/include/clang/Basic/BuiltinsRI

[PATCH] D154616: [RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.

This revision was automatically updated to reflect the committed changes. Closed by commit rG599421ae36c3: [RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

craig.topper updated this revision to Diff 540714. craig.topper added a comment. Rebase. Will merge tests next. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154647/new/ https://reviews.llvm.org/D154647 Files: clang/include/clang/Basic/BuiltinsR

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

craig.topper updated this revision to Diff 540716. craig.topper added a comment. Merge identical tests Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154647/new/ https://reviews.llvm.org/D154647 Files: clang/include/clang/Basic/BuiltinsRISCV.def

[PATCH] D155222: [RISCV][AArch64][IRGen] Add scalable->fixed as a special case in CreateCoercedStore.

craig.topper added a comment. In D155222#4505008 , @c-rhodes wrote: > It's been a while since I've looked at this code, what about this wouldnt > work for predicates? I seem to recall fixed predicates using i8 vs i1 for > scalable, is that issue? Happy

[PATCH] D155222: [RISCV][AArch64][IRGen] Add scalable->fixed as a special case in CreateCoercedStore.

craig.topper added a comment. I wonder if we should do something earlier `CodeGenFunction::EmitCall` before the call to CreateCoerecedStore and not go through memory at all? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155222/new/ https://reviews

[PATCH] D155220: [IRGen] Remove 'Sve' from the name of some IR names that are shared with RISC-V now.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGe8dc9dcd7df7: [IRGen] Remove 'Sve' from the name of some IR names that are shared with RISC-V… (authored by craig.topper). Repository: rG LLVM Git

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

craig.topper added a comment. Update ReleaseNotes? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa64b3e92c7cb: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types. (authored by craig.topper). Repository: rG LLVM Github Monore

[PATCH] D155495: [RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector.

craig.topper created this revision. craig.topper added reviewers: bsmith, sdesmalen, c-rhodes, joechrisellis. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbe

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

craig.topper added a comment. In D152279#4612087 , @MaskRay wrote: > I am still interested in moving this forward. What should be done here? If > the decision is to keep the current odd default 8 for > `toolchains::RISCVToolChain`, I guess I'll have to

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

craig.topper created this revision. craig.topper added reviewers: wangpc, kito-cheng, asb, reames, jrtc27. Herald added subscribers: jobnoorman, luke, sunshaoce, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mar

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:185 + FeatureStdExtZbb, + FeatureUnalignedScalarMem], [TuneSiFive7,

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

craig.topper updated this revision to Diff 554561. craig.topper added a comment. Remove change to sifive-x280. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159145/new/ https://reviews.llvm.org/D159145 Files: clang/lib/Driver/ToolChains/Arch/RIS

[PATCH] D158255: [RISCV][NFC] Update compile options for some vector crypto C intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158255/new/ https://reviews.llvm.org/D158255 ___

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

This revision was automatically updated to reflect the committed changes. Closed by commit rGc9db799dda69: [RISCV] Don't add -unaligned-scalar-mem to target features by default. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

craig.topper added inline comments. Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:479 + // 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`, + // `unsigned long long` and `double` to have 4-bytes alignment. This + // behavior may be changed when RV32E/ILP32

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. Can you link to a specification? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827 {{"zvfh"}, {ImpliedExtsZvfh}}, +{{"zvkb"}, {ImpliedExtsV}}, +{{"zvkg"}, {ImpliedExtsV}}, Does Crypto really require V or could it work with Zve? Repository: rG

[PATCH] D138930: [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version

craig.topper added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:266 // CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64 +// CHECK-ZVE64D-EXT: __riscv_v_intrinsic 1 // CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64 Check to end of line like th

[PATCH] D139025: [NFC][RISCV] Extract utility to calculate value through MajorVersion and MinorVersion

craig.topper added a comment. In D139025#3961990 , @eopXD wrote: > In D139025#3961214 , @jrtc27 wrote: > >> Should this live in RISCVISAInfo.h rather than be a Clang-specific thing >> given it's just for squeezin

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. Anything that uses OP-P needs to have a DecoderNamespace assigned and RISCVDisassembler::getInstruction will need to lookup that table when V/Zve is enabled. Otherwise we will have a conflict if the P extension is ever commited to LLVM. Comment

[PATCH] D76525: Expose cache line size in __builtin_get_cpu_cache_line_size

craig.topper added a comment. What should the behavior of the builtin be if the calling function has its own target cpu like __attribute__((target("arch=sandybridge"))) and that CPU has a different size than the CPU that was passed on the command line? Comment at: clang/inclu

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1786 +// i386 +case CK_i386: +// Netburst zoecarver wrote: > craig.topper wrote: > > I found the documentation for the 82385 cache controller chip for the 386. > > It's a

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added a comment. In D74918#1937291 , @lebedev.ri wrote: > In D74918#1937237 , @zoecarver wrote: > > > @lebedev.ri Where should I put this? Could you maybe point me to another > > LLVM target API that c

[PATCH] D76525: Expose cache line size in __builtin_get_cpu_cache_line_size

craig.topper added a comment. In D76525#1942825 , @zoecarver wrote: > @craig.topper I'm not sure what should happen. It should probably just use > that CPU (although that's not a great solution). Is there a way to detect if > an attribute was used to cha

[PATCH] D77193: [X86] Add SERIALIZE instruction.

craig.topper requested changes to this revision. craig.topper added inline comments. This revision now requires changes to proceed. Comment at: clang/lib/Headers/serializeintrin.h:17 + +static __inline__ void +__attribute__((__always_inline__, __nodebug__, __target__("serialize")

[PATCH] D77193: [X86] Add SERIALIZE instruction.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77193/new/ https://reviews.llvm.org/D77193 ___

[PATCH] D77193: [X86] Add SERIALIZE instruction.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77193/new/ https://reviews.llvm.org/D77193 ___ cfe-commits mailing list c

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77205/new/ https://reviews.llvm.org/D77205 ___

[PATCH] D76812: [X86] Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI) [3/3]

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86IndirectThunks.cpp:97 + void populateThunk(MachineFunction &MF) { +// This code mitigates LVI by replacing each indirect call/jump with a direct +// call/jump to a thunk that looks like:

[PATCH] D76812: [X86] Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI) [3/3]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76812/new/ https://reviews.llvm.org/D76812 ___ cfe-commits mailing list c

[PATCH] D76812: [X86] Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI) [3/3]

This revision was automatically updated to reflect the committed changes. Closed by commit rG5b519cf1fc67: [X86] Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI) (authored by sconstab, committed by craig.topper). Herald added a project: clang. Changed prior to commit: h

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1738 +// ++-+--

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1834 +case CK_Tigerlake: +case CK_Lakemont: + I think Lakemont is 16 bytes. Assuming I'm interpretting the CLFLUSH line size from this CPUID dump correctly https://github.co

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1738 +// ++-+--

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1834 +case CK_Tigerlake: +case CK_Lakemont: + zoecarver wrote: > craig.topper wrote: > > zoecarver wrote: > > > craig.topper wrote: > > > > I think Lakemont is 16 bytes. Assum

[PATCH] D74268: [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation

This revision was automatically updated to reflect the committed changes. Closed by commit rG727328433ad6: [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp… (authored by craig.topper). Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG L

[PATCH] D75162: [X86][F16C] Remove cvtph2ps intrinsics and use generic half2float conversion (PR37554)

craig.topper added a comment. Should we check that this generates constrained.fpext in strict mode? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75162/new/ https://reviews.llvm.org/D75162 ___ cfe-comm

[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1786 +// i386 +case CK_i386: +// Netburst I found the documentation for the 82385 cache controller chip for the 386. It's a bit weird. The tags for the cache are based on

[PATCH] D75162: [X86][F16C] Remove cvtph2ps intrinsics and use generic half2float conversion (PR37554)

craig.topper added a comment. In D75162#1896469 , @RKSimon wrote: > In D75162#1896365 , @craig.topper > wrote: > > > Should we check that this generates constrained.fpext in strict mode? > > > Sure - where is the b

[PATCH] D75162: [X86][F16C] Remove cvtph2ps intrinsics and use generic half2float conversion (PR37554)

craig.topper added a comment. I've posted https://reviews.llvm.org/D75304 to make the backend recognize the strict version of this pattern. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75162/new/ https://reviews.llvm.org/D75162 ___

[PATCH] D75162: [X86][F16C] Remove cvtph2ps intrinsics and use generic half2float conversion (PR37554)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75162/new/ https://reviews.llvm.org/D75162 ___

[PATCH] D75162: [X86][F16C] Remove cvtph2ps intrinsics and use generic half2float conversion (PR37554)

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:2551 - Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>; - def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">, - Intrinsic<[llvm_v8f32_ty],

[PATCH] D69756: [opaque pointer types] Add element type argument to IRBuilder CreatePreserveStructAccessIndex and CreatePreserveArrayAccessIndex

craig.topper created this revision. craig.topper added reviewers: jyknight, t.p.northover. Herald added subscribers: cfe-commits, arphaman. Herald added projects: clang, LLVM. These were the only remaining users of the GetElementPtrInst::getGEPReturnType method that gets the element type from the

[PATCH] D69756: [opaque pointer types] Add element type argument to IRBuilder CreatePreserveStructAccessIndex and CreatePreserveArrayAccessIndex

This revision was automatically updated to reflect the committed changes. Closed by commit rG910718bd038c: [opaque pointer types] Add element type argument to IRBuilder… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69756/

[PATCH] D69786: [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. Herald added subscribers: cfe-commits, jfb, hiraditya. Herald added projects: clang, LLVM. craig.topper added a reviewer: davezarzycki. -mvzeroupper will force the vzeroupper insertion pass to run on CPUs that norma

[PATCH] D69786: [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc.

craig.topper added a comment. In D69786#1731942 , @davezarzycki wrote: > Actually, wait, what does it mean for a CPU without AVX to have > `FeatureInsertVZEROUPPER`? Means we’ll do vzeroupper insertion if you add -mavx to the command line and ymm is u

[PATCH] D69786: [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc.

This revision was automatically updated to reflect the committed changes. Closed by commit rGb2b6a54f847f: [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D6

[PATCH] D69979: clang: Guess at some platform FTZ/DAZ default settings

craig.topper added a comment. I checked Redhat 7.4 that's on the server I'm using for work. And I had a coworker check his Ubuntu 18.04 system with this program. And both systems printed 1f80 as the value of MXCSR which shows FTZ and DAZ are both 0. Are you seeing something different? #inclu

[PATCH] D68627: [Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize.

craig.topper updated this revision to Diff 228511. craig.topper added a comment. Refactor to share more code with the CodeGen target feature stuff. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68627/new/ https://reviews.llvm.org/D68627 Files: clang/include/clang/AST/ASTContext.h c

[PATCH] D70101: [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit mode

craig.topper added a comment. In D70101#1741452 , @rnk wrote: > What do you think of using `__INTPTR_TYPE__` for this instead? If that > doesn't work, we could define and undefine our own macro to use as a typedef. > The resulting code should be clean en

[PATCH] D70101: [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit mode

craig.topper added a comment. So in order to match the long and int behavior, I need two different macros to replace the argument? I think __INTPTR_TYPE__ will return int on 32-bit targets so I can't use that for the long case. But maybe for the __int64? CHANGES SINCE LAST ACTION https://rev

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added reviewers: MaskRay, jyknight. craig.topper added a comment. Adding some others who may be be more familiar with the Fragments in the MC layer Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70157/new/ https://reviews.llvm.org/D701

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:134 + /// macro-fusion. + inline FirstMFInstKind classifyFirstOpcode(unsigned Opcode) { +switch (Opcode) { xiangzhangllvm wrote: > xiangzhangllvm wrote: > > We ra

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:88 +SmallVector BranchTypes; +StringRef(Val).split(BranchTypes, '-', -1, false); +for (auto BranchType : BranchTypes) { skan wrote: > chandlerc wrote: >

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:88 +SmallVector BranchTypes; +StringRef(Val).split(BranchTypes, '-', -1, false); +for (auto BranchType : BranchTypes) { skan wrote: > craig.topper wrote

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added a comment. I've definitely passed something like -Wl,--plugin-opt=-debug-only=isel,dagcombine on the command line before. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70157/new/ https://reviews.llvm.org/D70157 __

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added a comment. In D70157#1745127 , @skan wrote: > In D70157#1745125 , @craig.topper > wrote: > > > I've definitely passed something like > > -Wl,--plugin-opt=-debug-only=isel,dagcombine on the comma

[PATCH] D70101: [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit mode

craig.topper updated this revision to Diff 229372. craig.topper added a comment. Add __LPTRINT_TYPE__ and use that to qualify the readcr3. Use __INTPTR_TYPE__ for writecr3 CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70101/new/ https://reviews.llvm.org/D70101 Files: clang/lib/Heade

[PATCH] D70101: [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit mode

This revision was automatically updated to reflect the committed changes. Closed by commit rG3cec2a17de74: [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit mode (authored by craig.topper). Herald added a project: clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added a comment. In D70157#1747726 , @davezarzycki wrote: > In D70157#1747640 , @jyknight wrote: > > > In D70157#1747551 , @davezarzycki > > wrote: > > > > > I

[PATCH] D70348: Add header guards for header files that should not be included on the PS4 platform

craig.topper added a comment. You could probably just define add __ORBIS__ to every line and then rely on the individual feature defines at the end of the line to re-enable the ones that are really supported. I assume the target-cpu is set to btver for ps4? Comment at: clang/

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added a comment. In D70157#1755927 , @jyknight wrote: > Thanks for the comments, they help a little. But it's still somewhat > confusing, so let me write down what seems to be happening: > > - Before emitting every instruction, a new MCMachin

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:158 +case X86::AND16i16: +case X86::AND16mr: +case X86::AND16ri: None of the AND/ADD/SUB instructions ending in mr are eligible for macrofusion as far as I

[PATCH] D70157: Align branches within 32-Byte boundary

craig.topper added a comment. Can you please put the macro fusion changes in a separate phabricator review. I’ll review it in the morning US time and if it all looks good we can get that part committed while the other comments are being addressed. CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D68627: [Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize.

This revision was automatically updated to reflect the committed changes. Closed by commit rGe1578fd2b79f: [Sema][X86] Consider target attribute into the checks in validateOutputSize and… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D71159: [Attr] Move ParsedTargetAttr out of the TargetAttr class

craig.topper created this revision. craig.topper added reviewers: rnk, echristo, erichkeane. Need to forward declare it in ASTContext.h for D68627 , so it can't be a nested struct. https://reviews.llvm.org/D71159 Files: clang/include/clang/AST/Attr.h clang/

[PATCH] D71159: [Attr] Move ParsedTargetAttr out of the TargetAttr class

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: clang/include/clang/AST/Attr.h:359 } } // end namespace clang There's an ending namespace comment here and there's no namespace starting since the end of my chan

[PATCH] D71159: [Attr] Move ParsedTargetAttr out of the TargetAttr class

This revision was automatically updated to reflect the committed changes. Closed by commit rG505aa2410db6: [Attr] Move ParsedTargetAttr out of the TargetAttr class (authored by craig.topper). Herald added a project: clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D71467: [FPEnv] Generate constrained FP comparisons from clang

craig.topper added a subscriber: erichkeane. craig.topper added a comment. In D71467#1784286 , @rjmccall wrote: > The bug with `__builtin_isless` should be a really easy fix; the builtin just > needs to be flagged as having custom type-checking, and then

[PATCH] D62731: Add support for options -frounding-math, -ftrapping-math, -ffp-model=, and -ffp-exception-behavior=, : Specify floating point behavior

craig.topper added a comment. In D62731#1784491 , @pengfei wrote: > >> It's good that people are looking at achieving better modeling for the x86 > >> backend, but we need to have a plan that doesn't require heroic effort > >> just to get basic correctne

[PATCH] D71718: [X86] Mark various pointer arguments in builtins as const

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71718/new/ https://reviews.llvm.org/D71718 ___ cfe-commits mailing list c

[PATCH] D68627: [Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize.

This revision was automatically updated to reflect the committed changes. Closed by commit rGd35bcbbb5dab: [Sema][X86] Consider target attribute into the checks in validateOutputSize and… (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D68627?vs=232666&id=235168#to

[PATCH] D68627: [Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize.

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:116 class ObjCTypeParamDecl; +class ParsedTargetAttr; class Preprocessor; MaskRay wrote: > This should be `struct`. I fixed it it

[PATCH] D62731: Add support for options -frounding-math, -ftrapping-math, -ffp-model=, and -ffp-exception-behavior=, : Specify floating point behavior

craig.topper added a comment. In D62731#1796962 , @AntonYudintsev wrote: > I have found bug in clang-cl (win32 clang), related to recent inroduction of > ffp-exception-behavior. > Unfortunately, I don't have a working patch yet, and since LLVM bugtracke

[PATCH] D75723: [X86] Make intrinsics _BitScan* not limited to Windows

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsX86.def:1904 +// BITSCAN +TARGET_BUILTIN(_BitScanForward, "UcUNi*UNi", "n", "") +TARGET_BUILTIN(_BitScanReverse, "UcUNi*UNi", "n", "") The N specifier here is sort of MSVC mode spec

[PATCH] D75723: [X86] Make intrinsics _BitScan* not limited to Windows

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsX86.def:1904 +// BITSCAN +TARGET_BUILTIN(_BitScanForward, "UcUNi*UNi", "n", "") +TARGET_BUILTIN(_BitScanReverse, "UcUNi*UNi", "n", "") skan wrote: > craig.topper wrote: > > The N sp

[PATCH] D75723: [X86] Enable intrinsics _BitScan*

craig.topper added inline comments. Comment at: clang/lib/Headers/ia32intrin.h:419 +*(a) = (unsigned)__bsfd((int)(b)); \ +(unsigned char)((b) != 0); \ + }) this eva

[PATCH] D75894: [X86] Support intrinsics _bextr2*

craig.topper added inline comments. Comment at: clang/lib/Headers/bmiintrin.h:367 +} /// Clears all bits in the source except for the least significant bit ///containing a value of 1 and returns the result. Add a blank line here Repository: rG LLVM Gith

[PATCH] D75897: [X86] Support intrinsic _mm_broadcastsi128_si256

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75897/new/ https://reviews.llvm.org/D75897 ___

[PATCH] D75896: [X86] Support intrinsic _mm_cldemote

craig.topper added inline comments. Comment at: clang/lib/Headers/cldemoteintrin.h:27 +/// +/// This intrinsic corresponds to the CLDRMOTE instruction. static __inline__ void __DEFAULT_FN_ATTRS CLDRMOTE->CLDEMOTE Repository: rG LLVM Github Monorepo CHANGE

[PATCH] D75934: Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI)

craig.topper added inline comments. Comment at: clang/include/clang/Driver/Options.td:2295 Group, Flags<[CoreOption]>; +def mlvi_cfi : Flag<["-"], "mlvi-cfi">, Group, Flags<[CoreOption,DriverOption]>; +def mno_lvi_cfi : Flag<["-"], "mno-lvi-cfi">, Group, Flags<[CoreOption,Dr

[PATCH] D75723: [X86] Enable intrinsics _BitScan*

craig.topper added inline comments. Comment at: clang/lib/Headers/ia32intrin.h:418 + __extension__({ \ +*(a) = (unsigned)__bsfd((int)(b)); \ +(unsigned char)((b) != 0);

[PATCH] D75723: [X86] Enable intrinsics _BitScan*

craig.topper added inline comments. Comment at: clang/lib/Headers/ia32intrin.h:456 + __extension__({ \ +long long c = (long long)(b); \ +unsigned char d;

[PATCH] D75894: [X86] Support intrinsics _bextr2*

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75894/new/ https://reviews.llvm.org/D75894 ___

[PATCH] D75723: [X86] Enable intrinsics _BitScan*

craig.topper added inline comments. Comment at: clang/lib/Headers/ia32intrin.h:417 +#define _BitScanForward(a, b) \ + __extension__({ \ +int c = (int)(b);

[PATCH] D75896: [X86] Support intrinsic _mm_cldemote

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75896/new/ https://reviews.llvm.org/D75896 ___

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