craig.topper added inline comments.
================
Comment at: llvm/lib/Target/X86/X86.td:243
+ "Support SHA512 instructions",
+ [FeatureAVX]>;
// Processor supports CET SHSTK - Control-Flow Enforcement Technology
----------------
AVX2 like other integer features?
================
Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8304
+ [(set VR256:$dst,
+ (int_x86_vsha512msg1 VR256:$src1, VR128:$src2))]>, VEX_L,
+ VEX, T8XD, Sched<[WriteVecIMul]>;
----------------
This paren should be indented 1 more space so that it's not at the same column
as the one above it.
================
Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8310
+ [(set VR256:$dst,
+ (int_x86_vsha512msg2 VR256:$src1, VR256:$src2))]>, VEX_L,
+ VEX, T8XD, Sched<[WriteVecIMul]>;
----------------
ditto
================
Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8316
+ [(set VR256:$dst,
+ (int_x86_vsha512rnds2 VR256:$src1, VR256:$src2,
VR128:$src3))]>,
+ VEX_L, VEX_4V, T8XD, Sched<[WriteVecIMul]>;
----------------
ditto
================
Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:214
FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
+ FeatureSHA512 |
FeatureAMX_COMPLEX;
----------------
Unnecessary line break
================
Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:659
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
+constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX;
constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
----------------
Should this be AVX2 like all the other integer features?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155146/new/
https://reviews.llvm.org/D155146
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