https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/5] [RISCV][VLS] Support RISCV VLS calling convention
This patch a
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/99763
This prevent the warning from compiler.
>From faf331e112ddd7ab6633f5fced55cceaef7065e0 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Add a break t
4vtomat wrote:
> Should we use unreachable If it's not possible to suppress the warning from
> gcc?
>
> https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations
Maybe, but I just want to keep the original semantic here since if the case wa
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
Would it break if the case is not presented if we
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/99763
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@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
I mean, it's not supposed to crash if the case is
4vtomat wrote:
> Ah, it looks like we had another set of these. I just filed #99901 after a
> similar issue was reported in LLD.
Thanks for filing this!
https://github.com/llvm/llvm-project/pull/99763
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@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
I guess it won't get into `Type::Record` if it fal
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/99763
>From 97dff508a361bbab478735eb4bf186d698649acf Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Add a default case to nested switch in
`encodeTypeForF
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
Do you mean we should allow it to work if someone
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
I also agree with you that it should not reach the
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/99763
>From f4292accb12bcd2dbe951079cf2601f867bb4f96 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Make the end of the switch unreachable in
`encodeTypeF
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/99763
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/99763
>From 1ca71c8ed8b9f0cee9887ad81c03fd6a502f Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Make the end of the switch case unreachable in
`encode
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/89354
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89867
Since the minimum requirement is EEW=32, it's impossible that EGW=128
needs LMUL=8.
>From 1ed74c3732194512da7eee2e16bc252269f0e6ef Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 23 Apr 2024 20:42:33 -0700
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/89867
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/89867
>From 4db9d00610f110a163a1b7d5b168461f6a91f4ed Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 23 Apr 2024 20:42:33 -0700
Subject: [PATCH] [clang][RISCV] Remove LMUL=8 scalar input for some vector
crypto in
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89883
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable ve
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/89883
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/89883
>From 671bebcb9ad76aa3b43dabada3ab7a75d6934d73 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/2] [Clang][RISCV] Handle RVV tuple types correctly as
InputOperand/Outp
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/89883
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4vtomat wrote:
Ping.
https://github.com/llvm/llvm-project/pull/89883
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/106359
The C intrinsic spec is ratified:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234.
>From 59157100eac32981821eb15bce55d58f5f964bac Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 28 Aug 2024 0
4vtomat wrote:
> Do we still need this?
>
> ```
> def Experimental
>: SubtargetFeature<"experimental", "HasExperimental",
> "true", "Experimental intrinsics">;
> ```
I guess we do in case there is any other extension that encounter the same
situation lol~
https://git
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/106485
None
>From 71c66235e06faa0a793f829276991832ce5e487c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 28 Aug 2024 20:21:59 -0700
Subject: [PATCH] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp.
N
@@ -733,7 +733,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return Diag(TheCall->getBeginLoc(),
diag::err_riscv_builtin_requires_extension)
- << /* IsExtension */ tru
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/106359
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/106914
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable
@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">;
// Shadow Stack register
def SSP: RISCVReg<0, "ssp">;
-// Dummy VCIX state register
+// Dummy VCIX state register and its register class
def VCIX_STATE : RISCVReg<0, "vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32
4vtomat wrote:
> I would suggest it should prefix with a vendor prefix, either `sf.vcix_state`
> or `sifive.vcix_state`, also go `riscv-c-api-doc` or
> `riscv-toolchain-conventions` :)
Do you mean change the current `vcix_state` register to `sf.vcix_state`?
https://github.com/llvm/llvm-projec
4vtomat wrote:
> > Do you mean change the current vcix_state register to sf.vcix_state?
>
> Yes, because it's SiFive specific register, other vendor may add other status
> register like VCIX in future, so I would like to add prefix to make sure all
> further similar stuff will follow same rule
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/106914
>From 32126871d3dae79edaaa03bd1760790ca8a42e84 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:35:34 -0700
Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test
---
llvm/test/CodeGen/RISCV/inlin
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/106914
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https://github.com/4vtomat approved this pull request.
LGTM～
https://github.com/llvm/llvm-project/pull/90879
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/91556
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024
4vtomat wrote:
> Need to update RISCVUsage.rst and ReleaseNotes.rst
Is it going to be cherry-picked to release branch?
https://github.com/llvm/llvm-project/pull/91556
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/2] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified inform
4vtomat wrote:
> > > Need to update RISCVUsage.rst and ReleaseNotes.rst
> >
> >
> > Is it going to be cherry-picked to release branch?
>
> No. We just try to update the ReleaseNotes proactively for LLVM 19.
Got it!
https://github.com/llvm/llvm-project/pull/91556
_
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/92644
The NumVectors other than 1 is handled by the code above.
>From 4dbcf6e577d5f1aea0cde72e3a5a7fd73620b2d9 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 18 May 2024 03:07:43 -0700
Subject: [PATCH] [RISCV]
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/92644
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@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
4vtomat wrote:
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/3] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified inform
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/4] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified inform
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/91556
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4vtomat wrote:
Do we want vget/vset/vcreate/vundefined use `zvfhmin` rather than `zvfh`?
https://github.com/llvm/llvm-project/pull/101540
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https://github.com/4vtomat approved this pull request.
LGTM~
https://github.com/llvm/llvm-project/pull/101540
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101611
These two intrinsics are supported for f16 with `zvfhmin`, also support
them in bf16 to make it aligned to f16.
>From 53a18518189239643fade3cb6c636ebf1e4351da Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Th
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/101611
>From 53a18518189239643fade3cb6c636ebf1e4351da Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 21:05:12 -0700
Subject: [PATCH 1/2] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics
with `zv
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/101608
>From e12d3e8d28bc9d26bf3f5425841c00d95840a8f2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 20:21:01 -0700
Subject: [PATCH 1/2] [RISCV][sema] Correct the requirement of `vfcvt.f.*`
intrinsics
4vtomat wrote:
Reword
https://github.com/llvm/llvm-project/pull/101608
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/101608
>From 47a757769f5f1a25861227167c8409dd53875eaa Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 20:21:01 -0700
Subject: [PATCH 1/2] [RISCV][sema] Correct the requirement of
`vf[|n|w]cvt.f.*` intr
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/101608
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4vtomat wrote:
> What about vfncvt and vfwcvt?
Added!
https://github.com/llvm/llvm-project/pull/101608
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@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"v
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"v
@@ -1912,8 +1912,12 @@ def vfcvt_rtz_x_f_v :
RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
- def
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"v
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"v
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/101608
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@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"v
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/101608
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https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/101633
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101643
`vundefined` doesn't have corresponding named IR, instead it generates
`poison` value, we already define the `Name` for C intrinsics, so we
don't need the defining name at all.
>From df6b40a85ca89259751583b6642
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101646
We don't have `fp8` type supported yet.
>From ff5083431d41d22c50725638b084bfb2532dad74 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 2 Aug 2024 03:04:18 -0700
Subject: [PATCH] [RISCV][clang] Remove unus
4vtomat wrote:
> Make sense to me.
> (Do we have a way to test these generated builtins?)
I think we don't since the intrinsics are generated on demand during runtime.
https://github.com/llvm/llvm-project/pull/101646
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4vtomat wrote:
> I don't think this will be better. We may keep these names so that these code
> can be self-explanatory.
Yeah, it's reasonable to me.
https://github.com/llvm/llvm-project/pull/101643
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https://github.com/llvm/llvm-project/pull/101643
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https://github.com/4vtomat approved this pull request.
LGTM~
https://github.com/llvm/llvm-project/pull/101733
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4vtomat wrote:
This has been resolved by: https://github.com/llvm/llvm-project/pull/101733
https://github.com/llvm/llvm-project/pull/101608
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101811
Fix https://github.com/llvm/llvm-project/issues/101526
`vf[n|w]cvt.x[|u].f` for f16 needs `zvfh` instead of `zvfhmin`, current approach
is not able to detect this. Ultimately we need to add `zvfh` to RequiredFea
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/101611
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https://github.com/llvm/llvm-project/pull/102146
None
>From 9ca5156a494d7f88ea80a960e2515142ae867ba8 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 6 Aug 2024 06:56:48 -0700
Subject: [PATCH] [RISCV][clang] Remove bfloat base type in non-zvfbfmin
vcreat
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/102149
It's missing in the patch supporting `zvfbfmin` intrinsics.
>From 17cbf0b868699a04639c49acf4bbf383e70e85ca Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 6 Aug 2024 07:06:13 -0700
Subject: [PATCH] [RISCV
@@ -2206,6 +2206,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
<< A->getSpelling() << Val;
}
}
+
+ if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ)) {
+StringRef ABIVLenStr = A->getValue();
+unsigned ABIVLen;
+const Driver &
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/6] [RISCV][VLS] Support RISCV VLS calling convention
This patch a
4vtomat wrote:
> Make sense to me. It was wrong since when?
It's from the tuple interface change patches,
https://github.com/llvm/llvm-project/pull/97992.
https://github.com/llvm/llvm-project/pull/111476
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4vtomat wrote:
> Why don’t any of our lit tests that use every intrinsic catch it?
Somehow if we add more "target-feature" the intrinsics increase, I'm not sure
why.
For example:
```
test.c
#include "riscv_vector.h"
vfloat16mf4x7_t test_vlseg7e16ff_v_f16mf4x7(const _Float16 *base, size_t
*n
4vtomat wrote:
> > > Why don’t any of our lit tests that use every intrinsic catch it?
>
> >
>
> > Somehow if we add more "target-feature" the intrinsics increase, I'm not
> > sure why. For example:
>
> >
>
> > ```
>
> > test.c
>
> >
>
> > #include "riscv_vector.h"
>
> > vfloat16mf4
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/111466
It's illegal if the index is 64 bits and is zero-extend to 32 bits.
>From 6e11ffa9585cf189382501d44915f211abd4be46 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 7 Oct 2024 19:33:41 -0700
Subject: [PATCH
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/111466
>From cd79ab5782175de38adfa6b171270766d2544204 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 7 Oct 2024 19:33:41 -0700
Subject: [PATCH] [clang][RISCV] Make the index of riscv_tuple_extract and
riscv_tupl
4vtomat wrote:
> test?
Added!
https://github.com/llvm/llvm-project/pull/111466
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4vtomat wrote:
> I think we need to change
>
> ```
> struct RVVOverloadIntrinsicDef {
> // Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
> SmallVector Indexes;
> };
> ```
>
> and
>
> ```
> // Mapping function name to index of IntrinsicList.
> StringMap Intrinsics;
> ```
>
> Tho
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/111481
>From 832a7576ad864aeaf8f183b631d1d805497aebf5 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 7 Oct 2024 22:03:43 -0700
Subject: [PATCH 1/2] [clang][RISCV] Extend intrinsic size check variable from
16 ->
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/111466
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/111481
We currently have over 67000 intrinsics, uint16_t will overflow.
>From f6a27f7de2459e22961555054b92a61a0e7ededf Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 7 Oct 2024 22:03:43 -0700
Subject: [PATCH] [
@@ -317,38 +323,60 @@ ABIArgInfo
RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
// Fixed-length RVV vectors are represented as scalable vectors in function
// args/return and must be coerced from fixed vectors.
-ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {
https://github.com/4vtomat approved this pull request.
Somehow I missed [this](https://github.com/llvm/llvm-project/issues/94306)
issue, thanks for fixing this!
https://github.com/llvm/llvm-project/pull/115436
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From 1c8201daa6925cac510ff8751ffd79a6b95f2315 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/2] [RISCV][VLS] Support RISCV VLS calling convention
This patch a
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/115657
This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pull/1564
The spec states that the `svukte` depends on `sv39`,
4vtomat wrote:
The spec is frozen, but the PR is still version 0.3, I'll follow the spec to
update the version.
https://github.com/llvm/llvm-project/pull/115657
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https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/115657
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/106914
>From be771da74a7663d56cdf850c10b4daa47c087bcc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:35:34 -0700
Subject: [PATCH 1/3] [RISCV][VCIX] Precommit test
---
llvm/test/CodeGen/RISCV/inlin
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