https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/101608
>From 47a757769f5f1a25861227167c8409dd53875eaa Mon Sep 17 00:00:00 2001 From: Brandon Wu <brandon...@sifive.com> Date: Thu, 1 Aug 2024 20:21:01 -0700 Subject: [PATCH 1/2] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics Fix https://github.com/llvm/llvm-project/issues/101526 `vf[|n|w]cvt.f.*` for f16 needs `zvfh` instead of `zvfhmin`, current approach is not able to detect this. Ultimately we need to add `zvfh` to RequiredFeatures to check other intrinsics instead, the type check should be done in checkRVVTypeSupport. --- clang/include/clang/Basic/riscv_vector.td | 20 +++++++++++++++---- .../clang/Support/RISCVVIntrinsicUtils.h | 3 ++- clang/lib/Sema/SemaRISCV.cpp | 6 ++++++ clang/utils/TableGen/RISCVVEmitter.cpp | 1 + 4 files changed, 25 insertions(+), 5 deletions(-) diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index a0820e2093bc2..93617b3e28429 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1987,9 +1987,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvvu"]]>; let OverloadedName = "vfcvt_f" in { defm : - RVVConvBuiltinSet<"vfcvt_f_x_v", "sil", [["Fv", "Fvvu"]]>; + RVVConvBuiltinSet<"vfcvt_f_x_v", "il", [["Fv", "Fvvu"]]>; defm : - RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUvu"]]>; + RVVConvBuiltinSet<"vfcvt_f_xu_v", "il", [["Fv", "FvUvu"]]>; + let RequiredFeatures = ["Zvfh"] in { + defm : + RVVConvBuiltinSet<"vfcvt_f_x_v", "s", [["Fv", "Fvvu"]]>; + defm : + RVVConvBuiltinSet<"vfcvt_f_xu_v", "s", [["Fv", "FvUvu"]]>; + } } // 13.18. Widening Floating-Point/Integer Type-Convert Instructions @@ -2037,9 +2043,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvv"]]>; let OverloadedName = "vfcvt_f" in { defm : - RVVConvBuiltinSet<"vfcvt_f_x_v", "sil", [["Fv", "Fvv"]]>; + RVVConvBuiltinSet<"vfcvt_f_x_v", "il", [["Fv", "Fvv"]]>; defm : - RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUv"]]>; + RVVConvBuiltinSet<"vfcvt_f_xu_v", "il", [["Fv", "FvUv"]]>; + let RequiredFeatures = ["Zvfh"] in { + defm : + RVVConvBuiltinSet<"vfcvt_f_x_v", "s", [["Fv", "Fvv"]]>; + defm : + RVVConvBuiltinSet<"vfcvt_f_xu_v", "s", [["Fv", "FvUv"]]>; + } } // 13.18. Widening Floating-Point/Integer Type-Convert Instructions diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index b4ff61784126e..9a6a2092eb996 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -502,7 +502,8 @@ enum RVVRequire : uint32_t { RVV_REQ_Zvksh = 1 << 15, RVV_REQ_Zvfbfwma = 1 << 16, RVV_REQ_Zvfbfmin = 1 << 17, - RVV_REQ_Experimental = 1 << 18, + RVV_REQ_Zvfh = 1 << 18, + RVV_REQ_Experimental = 1 << 19, LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental) }; diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index f1c7c0516e671..abf8e4ac2f3e8 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -222,6 +222,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( {"zvksh", RVV_REQ_Zvksh}, {"zvfbfwma", RVV_REQ_Zvfbfwma}, {"zvfbfmin", RVV_REQ_Zvfbfmin}, + {"zvfh", RVV_REQ_Zvfh}, {"experimental", RVV_REQ_Experimental}}; // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics @@ -280,6 +281,11 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI) continue; + // TODO: Remove the check below and use RequiredFeatures in + // riscv_vector.td to check the intrinsics instead, the type check should + // be done in checkRVVTypeSupport. This check also not able to work on the + // intrinsics that have Float16 but the BaseType is not Float16 such as + // `vfcvt_f_x_v`. if (BaseType == BasicType::Float16) { if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) { if (!TI.hasFeature("zvfhmin")) diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 7f3cb70c97d09..ef7159fae9fd2 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -670,6 +670,7 @@ void RVVEmitter::createRVVIntrinsics( .Case("Zvksh", RVV_REQ_Zvksh) .Case("Zvfbfwma", RVV_REQ_Zvfbfwma) .Case("Zvfbfmin", RVV_REQ_Zvfbfmin) + .Case("Zvfh", RVV_REQ_Zvfh) .Case("Experimental", RVV_REQ_Experimental) .Default(RVV_REQ_None); assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?"); >From 3660544a042fdc444d601142c21712e3a239e763 Mon Sep 17 00:00:00 2001 From: Brandon Wu <brandon...@sifive.com> Date: Thu, 1 Aug 2024 21:53:00 -0700 Subject: [PATCH 2/2] fixup! add vfncvt and vfwcvt --- clang/include/clang/Basic/riscv_vector.td | 28 ++++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 93617b3e28429..2055385d6a5d7 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1912,8 +1912,12 @@ def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">; let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">; def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">; - def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">; - def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">; + def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "si", "vfwcvt_f">; + def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "si", "vfwcvt_f">; + let RequiredFeatures = ["Zvfh"], OverloadedName = "vfwcvt_f" in { + defm : RVVConvBuiltinSet<"vfwcvt_f_xu_v", "c", [["Fw", "FwUv"]]>; + defm : RVVConvBuiltinSet<"vfwcvt_f_x_v", "c", [["Fw", "Fwv"]]>; + } def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">; let RequiredFeatures = ["Zvfhmin"] in def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> { @@ -2017,9 +2021,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>; + RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvwu"]]>; defm : - RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUwu"]]>; + RVVConvBuiltinSet<"vfncvt_f_xu_w", "ci", [["Fv", "FvUwu"]]>; + let RequiredFeatures = ["Zvfh"] in { + defm : + RVVConvBuiltinSet<"vfncvt_f_x_w", "s", [["Fv", "Fvwu"]]>; + defm : + RVVConvBuiltinSet<"vfncvt_f_xu_w", "s", [["Fv", "FvUwu"]]>; + } } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>; @@ -2073,9 +2083,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFw"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvw"]]>; + RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvw"]]>; defm : - RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUw"]]>; + RVVConvBuiltinSet<"vfncvt_f_xu_w", "ci", [["Fv", "FvUw"]]>; + let RequiredFeatures = ["Zvfh"] in { + defm : + RVVConvBuiltinSet<"vfncvt_f_x_w", "s", [["Fv", "Fvw"]]>; + defm : + RVVConvBuiltinSet<"vfncvt_f_xu_w", "s", [["Fv", "FvUw"]]>; + } } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
