================
@@ -664,5 +664,9 @@ def FRM : RISCVReg<0, "frm">;
// Shadow Stack register
def SSP : RISCVReg<0, "ssp">;
-// Dummy VCIX state register
+// Dummy VCIX state register and its register class
def VCIX_STATE : RISCVReg<0, "vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add VCIX_STATE)> {
----------------
4vtomat wrote:
In `getRegForInlineAsmConstraint` if there would be no value in `AssignedRegs`
when calling `getRegistersForValue` for the `vcix_state` constraint, thus it
would be deprecated when constructing selectionDAG.
https://github.com/llvm/llvm-project/pull/106914
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
